-
公开(公告)号：US20130248887A1
公开(公告)日：2013-09-26
申请号：US13845445
申请日：2013-03-18
Inventor： Romain Coffy , Eric Saugier , Hk Looi , Norbert Chevrier
IPC: H01L31/0203 , H01L31/18
CPC classification number: H01L31/0203 , G01S7/481 , G01S17/026 , H01L25/167 , H01L31/18 , H01L2224/48091 , H01L2224/49175 , H01L2924/181 , H03K17/941 , H03K2017/9455 , H03K2217/94026 , H03K2217/94112 , H01L2924/00014 , H01L2924/00012
Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.
Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。
-
公开(公告)号：US09105766B2
公开(公告)日：2015-08-11
申请号：US13845445
申请日：2013-03-18
Inventor： Romain Coffy , Eric Saugier , Hk Looi , Norbert Chevrier
IPC: H01L33/48 , H01L31/0203 , H01L31/18 , G01S17/02 , H01L25/16 , H03K17/94 , G01S7/481 , H03K17/945
CPC classification number: H01L31/0203 , G01S7/481 , G01S17/026 , H01L25/167 , H01L31/18 , H01L2224/48091 , H01L2224/49175 , H01L2924/181 , H03K17/941 , H03K2017/9455 , H03K2217/94026 , H03K2217/94112 , H01L2924/00014 , H01L2924/00012
Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.
Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。
-
公开(公告)号：US09525094B2
公开(公告)日：2016-12-20
申请号：US14671707
申请日：2015-03-27
Inventor： Eric Saugier , Wing Shenq Wong , David Gani
CPC classification number: H01L31/167 , H01L25/167 , H01L31/02005 , H01L31/18 , H01L2224/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01S5/02248 , H01S5/0226 , H01S5/02276 , H01S5/183 , H01L2924/00014 , H01L2924/00
Abstract: A proximity sensor having a relatively small footprint includes a substrate, a semiconductor die, a light emitting device, and a cap. The light emitting device overlies the semiconductor die. The semiconductor die is secured to the substrate and includes a sensor area capable of detecting light from by the light emitting device. The cap also is secured to the substrate and includes a light barrier that prevents some of the light emitted by the light emitting device from reaching the sensor area. In one embodiment, the light emitting device and the semiconductor die are positioned on the same side of the substrate, wherein the light emitting device is positioned on the semiconductor die. In another embodiment, the light emitting device is positioned on one side of the substrate and the semiconductor die is positioned on an opposing side of the substrate.
Abstract translation: 具有相对较小占地面积的接近传感器包括衬底，半导体管芯，发光器件和帽。 发光器件覆盖半导体管芯。 半导体管芯被固定到基板上并且包括能够检测来自发光器件的光的传感器区域。 盖子也被固定到基板上并且包括防止由发光装置发射的一些光到达传感器区域的光栅。 在一个实施例中，发光器件和半导体管芯位于衬底的相同侧上，其中发光器件位于半导体管芯上。 在另一个实施例中，发光器件位于衬底的一侧，并且半导体管芯位于衬底的相对侧上。
-
公开(公告)号：US10978400B2
公开(公告)日：2021-04-13
申请号：US16390889
申请日：2019-04-22
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Eric Saugier
IPC: H01L23/538 , H01L21/768 , H01L23/498
Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.
-
5.发明授权公开(公告)号：US10483408B2
公开(公告)日：2019-11-19
申请号：US15689976
申请日：2017-08-29
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine Saxod , Alexandre Mas , Eric Saugier , Gaetan Lobascio , Benoit Besancon
IPC: H01L31/0203 , H01L31/18 , H01L31/0232 , H01L31/02 , H01L31/12 , B29C45/14 , H01L33/48 , B29L31/34
Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
-
Patent Agency Ranking
公开(公告)号：US20170345796A1
公开(公告)日：2017-11-30
申请号：US15391211
申请日：2016-12-27
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Eric Saugier
IPC: H01L25/065 , H01L23/538 , H01L21/822
Abstract: An electronic device includes a carrier substrate, a first electronic chip and a second chip. The first chip is mounted on the carrier substrate via interposed electrical connection elements electrically connecting a front electrical connection network of the first chip and an electrical connection network of the carrier substrate. The second chip is mounted on the first chip via interposed electrical connection elements electrically connecting a front electrical connection network of the second chip and a back electrical connection network of the first chip Electrical connection wires electrically connect the back electrical connection network of the first chip to the electrical connection network of the carrier substrate.
-
7.发明申请公开(公告)号：US20180190838A1
公开(公告)日：2018-07-05
申请号：US15689976
申请日：2017-08-29
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine Saxod , Alexandre Mas , Eric Saugier , Gaetan Lobascio , Benoit Besancon
IPC: H01L31/0203 , H01L31/18 , H01L31/0232 , H01L31/02 , H01L31/12 , B29C45/14
CPC classification number: H01L31/0203 , B29C45/14065 , B29C45/14639 , B29C45/14778 , B29K2995/0026 , B29L2031/3481 , H01L31/02002 , H01L31/02325 , H01L31/02327 , H01L31/12 , H01L31/18 , H01L33/483
Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
-
公开(公告)号：US20170256514A1
公开(公告)日：2017-09-07
申请号：US15238921
申请日：2016-08-17
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Eric Saugier
CPC classification number: H01L24/17 , H01L21/82 , H01L23/481 , H01L24/81 , H01L27/14618 , H01L27/14636 , H01L27/14638 , H01L27/14683 , H01L31/02 , H01L2924/14
Abstract: Electronic devices are collectively fabricated from a main wafer which includes optical elements and a secondary wafer that are mounted one on top of the other to form a combined wafer. A mounting face of the secondary wafer is mated to a front face of the main wafer in such a manner that recesses within the mounting face of the secondary wafer are aligned over the optical elements. The thickness of the secondary wafer reduced until the recesses are opened to form ring structures with openings at the recesses. The combined wafer is diced to form electronic devices. A base wafer of the main wafer and the secondary wafer are made of a same semiconductor material (for example, silicon).
-
9.发明授权公开(公告)号：US11688815B2
公开(公告)日：2023-06-27
申请号：US17081299
申请日：2020-10-27
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine Saxod , Alexandre Mas , Eric Saugier , Gaetan Lobascio , Benoit Besancon
IPC: H01L31/02 , H01L31/0203 , H01L31/18 , H01L31/0232 , H01L31/12 , B29C45/14 , H01L33/48 , B29L31/34
CPC classification number: H01L31/0203 , B29C45/14065 , B29C45/14639 , H01L31/02002 , H01L31/02325 , H01L31/02327 , H01L31/12 , H01L31/18 , H01L33/483 , B29C45/14778 , B29K2995/0026 , B29L2031/3481
Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
-
公开(公告)号：US10811349B2
公开(公告)日：2020-10-20
申请号：US16110121
申请日：2018-08-23
Inventor： David Auchere , Laurent Schwarz , Deborah Cogoni , Eric Saugier
IPC: H01L23/498 , H01L23/538 , H01L23/00 , H05K1/18 , H01L23/31 , H01L23/13 , H01L21/56 , H01L21/78
Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.016 seconds)
