公开(公告)号：US11977971B2

公开(公告)日：2024-05-07

申请号：US18167366

申请日：2023-02-10

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06T7/62 ,  G06F9/38 ,  G06F16/901 ,  G06F18/22 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06T7/11 ,  G06T15/08 ,  G06V10/82 ,  G06V20/00 ,  G06V10/75

CPC classification number: G06N3/063 ,  G06F9/3877 ,  G06F16/9024 ,  G06F18/22 ,  G06N3/045 ,  G06N3/08 ,  G06T7/11 ,  G06T7/62 ,  G06T15/08 ,  G06V10/82 ,  G06V20/00 ,  G06V10/759

Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

公开(公告)号：US11880759B2

公开(公告)日：2024-01-23

申请号：US18172979

申请日：2023-02-22

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Giuseppe Desoli ,  Carmine Cappetta ,  Thomas Boesch ,  Surinder Pal Singh ,  Saumya Suneja

IPC: G06N3/045 ,  G06F16/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/045 ,  G06F16/2282 ,  G06F18/217 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

公开(公告)号：US11740870B2

公开(公告)日：2023-08-29

申请号：US16833353

申请日：2020-03-27

Applicant: STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

Inventor： Giuseppe Desoli ,  Thomas Boesch ,  Carmine Cappetta ,  Ugo Maria Iannuzzi

IPC: G06F7/544 ,  G06N3/04

CPC classification number: G06F7/5443 ,  G06N3/04

Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.

公开(公告)号：US11726543B2

公开(公告)日：2023-08-15

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Anuj Grover ,  Giuseppe Desoli ,  Kedar Janardan Dhori ,  Thomas Boesch ,  Promod Kumar

IPC: G06F1/3234 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78 ,  G11C11/413 ,  G11C5/14 ,  G11C11/417 ,  G06F1/26

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US11610362B2

公开(公告)日：2023-03-21

申请号：US17194055

申请日：2021-03-05

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06T7/62 ,  G06T7/11 ,  G06T15/08 ,  G06F16/901 ,  G06F9/38 ,  G06K9/62 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06V20/00 ,  G06V10/82 ,  G06V10/75

Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

公开(公告)号：US12106201B2

公开(公告)日：2024-10-01

申请号：US17039653

申请日：2020-09-30

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Carmine Cappetta ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/04 ,  G06F9/38 ,  G06F13/16 ,  G06F13/40 ,  G06N3/063 ,  G06T7/11

CPC classification number: G06N3/04 ,  G06F9/3806 ,  G06F13/1657 ,  G06F13/1673 ,  G06F13/4022 ,  G06N3/063 ,  G06T7/11 ,  G06T2207/20084

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

公开(公告)号：US11586907B2

公开(公告)日：2023-02-21

申请号：US16280960

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal Singh ,  Giuseppe Desoli ,  Thomas Boesch

IPC: G06F9/02 ,  G06N3/08 ,  G06N20/00 ,  G06F17/11 ,  G06N3/04 ,  G06N3/063 ,  G06F9/30

Abstract: Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit, and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has a plurality of inputs and at least one output, and the arithmetic unit is solely dedicated to performance of a plurality of parallel operations. Each one of the plurality of parallel operations carries out a portion of the formula: output=AX+BY+C.

公开(公告)号：US11474788B2

公开(公告)日：2022-10-18

申请号：US16890870

申请日：2020-06-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：US11442700B2

公开(公告)日：2022-09-13

申请号：US16833340

申请日：2020-03-27

Applicant: STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

Inventor： Michele Rossi ,  Giuseppe Desoli ,  Thomas Boesch ,  Carmine Cappetta

IPC: G06F7/72 ,  H03M7/18

Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.

公开(公告)号：US11308406B2

公开(公告)日：2022-04-19

申请号：US15877138

申请日：2018-01-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Valentina Arrigoni ,  Giuseppe Desoli ,  Beatrice Rossi ,  Pasqualina Fragneto

IPC: G06N5/04 ,  G06F7/72 ,  G06N3/04 ,  G06F17/16 ,  G06N7/00 ,  G06N7/02

Abstract: A method of operating neural networks such as convolutional neural networks including, e.g., an input layer, an output layer and at least one intermediate layer between the input layer and the output layer, with the network layers including operating circuits performing arithmetic operations on input data to provide output data. The method includes: selecting a set of operating circuits in the network layers, performing arithmetic operations in operating circuits in the selected set of operating circuits by performing Residue Number System or RNS operations on RNS-converted input data by obtaining RNS output data in the Residue Number System, backward converting from the Residue Number System the RNS output data resulting from the RNS operations.