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公开(公告)号：US09911820B2
公开(公告)日：2018-03-06
申请号：US15464763
申请日：2017-03-21
Applicant: Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Cyrille Le Royer , Frederic Boeuf , Laurent Grenouillet , Louis Hutin , Yves Morand
IPC: H01L29/06 , H01L29/49 , H01L29/51 , H01L23/535 , H01L29/66 , H01L21/768
CPC classification number: H01L29/4983 , H01L21/76895 , H01L23/535 , H01L29/0649 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/66628
Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.
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公开(公告)号：US20160109732A1
公开(公告)日：2016-04-21
申请号：US14981139
申请日：2015-12-28
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Jean-Robert Manouvrier , Frederic Boeuf
IPC: G02F1/025
CPC classification number: G02F1/025 , G02F1/225 , G02F2001/212
Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.
Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。
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公开(公告)号：US20170271470A1
公开(公告)日：2017-09-21
申请号：US15464763
申请日：2017-03-21
Applicant: Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Cyrille LE ROYER , Frederic Boeuf , Laurent Grenouillet , Louis Hutin , Yves Morand
IPC: H01L29/49 , H01L21/768 , H01L29/06 , H01L29/66 , H01L29/51 , H01L23/535
CPC classification number: H01L29/4983 , H01L21/76895 , H01L23/535 , H01L29/0649 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/66628
Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.
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公开(公告)号：US11698296B2
公开(公告)日：2023-07-11
申请号：US17024202
申请日：2020-09-17
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： Stephane Monfray , Olivier Le Neel , Frederic Boeuf
IPC: G01J1/04 , H01L31/0232 , G01J1/44 , G02B5/18 , H01L31/101
CPC classification number: G01J1/0411 , G01J1/44 , G02B5/1828 , G02B5/1857 , H01L31/02327 , H01L31/1013 , G01J2001/444
Abstract: A light sensor includes a semiconductor substrate supporting a number of pixels. Each pixel includes a photoconversion zone extending in the substrate between a front face and a back face of the substrate. An optical diffraction grating is arranged over the back face of the substrate at a position facing the photoconversion zone of the pixel. For at least two different pixels of the light sensor, the optical diffraction gratings have different pitches. Additionally, the optical grating of each pixel is surrounded by an opaque wall configured to absorb at operating wavelengths of the sensor.
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公开(公告)号：US10126497B2
公开(公告)日：2018-11-13
申请号：US15377848
申请日：2016-12-13
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frederic Boeuf , Charles Baudot
Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
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Patent Agency Ranking
公开(公告)号：US20170336560A1
公开(公告)日：2017-11-23
申请号：US15377848
申请日：2016-12-13
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frederic Boeuf , Charles Baudot
CPC classification number: G02B6/12002 , G02B6/12004 , G02B6/122 , G02B6/124 , G02B6/126 , G02B6/2773 , G02B6/30 , G02B6/34 , G02B6/4204 , G02B2006/12104 , G02B2006/12107 , G02B2006/12116 , G02B2006/12147
Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
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公开(公告)号：US20180136496A1
公开(公告)日：2018-05-17
申请号：US15868642
申请日：2018-01-11
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Charles Baudot , Maurin Douix , Frederic Boeuf , Sébastien Cremer
CPC classification number: G02F1/025 , G02F2001/0151
Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
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公开(公告)号：US09653538B2
公开(公告)日：2017-05-16
申请号：US14220542
申请日：2014-03-20
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Frederic Boeuf , Olivier Weber
IPC: H01L21/00 , H01L21/762 , H01L21/02 , H01L29/78 , H01L21/84 , H01L21/324 , H01L29/06 , H01L27/12
CPC classification number: H01L29/7847 , H01L21/02381 , H01L21/02422 , H01L21/02532 , H01L21/02639 , H01L21/02667 , H01L21/76264 , H01L21/76283 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/12 , H01L27/1203 , H01L29/0611 , H01L29/0642 , H01L29/16 , H01L29/161 , H01L29/7838
Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
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公开(公告)号：US11329455B2
公开(公告)日：2022-05-10
申请号：US16867666
申请日：2020-05-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Mathias Prost , Moustafa El Kurdi , Philippe Boucaud , Frederic Boeuf
IPC: H01S5/227 , H01S5/32 , H01S5/02 , H01S5/042 , H01S5/30 , H01S5/10 , G02B6/136 , G02B6/12 , G02B6/10
Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
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公开(公告)号：US20210119416A1
公开(公告)日：2021-04-22
申请号：US16757308
申请日：2017-10-19
Applicant: STMicroelectronics (Crolles 2) SAS , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , Universite Paris-Saclay
Inventor： Anas Elbaz , Moustafa El Kurdi , Abdelhanin Aassime , Philippe Boucaud , Frederic Boeuf
Abstract: A structure includes a semiconductor support, a semiconductor region overlying the semiconductor support, a silicon nitride layer surrounding and straining the semiconductor region, and a metal foot separating the silicon nitride layer from the semiconductor support. The semiconductor region includes germanium. The semiconductor region can be a resonator of a laser or a waveguide.
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