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    Semiconductor integrated device assembly process
    1.
    发明授权
    Semiconductor integrated device assembly process 有权
    半导体集成器件组装过程

    公开(公告)号：US08921164B2

    公开(公告)日：2014-12-30

    申请号：US13772210

    申请日：2013-02-20

    Applicant: STMicroelectronics Ltd (Malta) ,  STMicroelectronics S.r.l.

    Inventor： Kenneth Fonk ,  Luca Maggi ,  Jeremy Spiteri

    IPC: H01L21/00 ,  H01L23/495

    CPC classification number: B81B7/0045 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00238 ,  B81C1/00325 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.

    Abstract translation: 集成装置的组装方法设想：提供集成至少一个电子电路并具有顶表面的第一半导体材料体; 提供集成至少一个微机电结构并具有底表面的第二半导体材料; 并且在所述第一主体的顶表面和所述第二主体的所述底表面之间插入所述第一主体上的所述第二主体的弹性间隔件材料。 在层叠步骤之前，该步骤被设想为以第一体积的方式在第一体的顶表面处提供约束和间隔结构，该限制和间隔结构在其内部限定弹性间隔物材料，并且将第二体与第一体 身体在堆叠步骤。

    SEMICONDUCTOR INTEGRATED DEVICE ASSEMBLY PROCESS
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED DEVICE ASSEMBLY PROCESS 有权
    半导体集成器件组装工艺

    公开(公告)号：US20130214368A1

    公开(公告)日：2013-08-22

    申请号：US13772210

    申请日：2013-02-20

    Applicant: STMicroelectronics Ltd (Malta) ,  STMicroelectronics S.r.l.

    Inventor： Kenneth Fonk ,  Luca Maggi ,  Jeremy Spiteri

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0045 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00238 ,  B81C1/00325 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.

    Abstract translation: 集成装置的组装方法设想：提供集成至少一个电子电路并具有顶表面的第一半导体材料体; 提供集成至少一个微机电结构并具有底表面的第二半导体材料; 并且在所述第一主体的顶表面和所述第二主体的所述底表面之间插入所述第一主体上的所述第二主体的弹性间隔件材料。 在层叠步骤之前，该步骤被设想为以第一体积的方式在第一体的顶表面处提供约束和间隔结构，该限制和间隔结构在其内部限定弹性间隔物材料，并且将第二体与第一体 身体在堆叠步骤。

    Photonic wafer level testing systems, devices, and methods of operation
    3.
    发明授权
    Photonic wafer level testing systems, devices, and methods of operation 有权

    公开(公告)号：US12216020B2

    公开(公告)日：2025-02-04

    申请号：US17318831

    申请日：2021-05-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marco Piazza ,  Antonio Canciamilla ,  Piero Orlandi ,  Luca Maggi

    IPC: G01M11/00 ,  G01M11/02 ,  G01R31/317 ,  G01R31/3185 ,  G02B6/293

    Abstract: A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.

    Photonic IC chip
    4.
    发明授权
    Photonic IC chip 有权

    公开(公告)号：US11269141B2

    公开(公告)日：2022-03-08

    申请号：US16821370

    申请日：2020-03-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Frédéric Boeuf ,  Luca Maggi

    IPC: G02B6/124 ,  G02B6/34 ,  G02B6/43 ,  G02B6/30 ,  G02B6/12 ,  G02B6/136

    Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

    Optical integrated circuit systems, devices, and methods of fabrication
    6.
    发明授权
    Optical integrated circuit systems, devices, and methods of fabrication 有权

    公开(公告)号：US10262984B1

    公开(公告)日：2019-04-16

    申请号：US16028263

    申请日：2018-07-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Luca Maggi ,  Piero Orlandi

    IPC: H01L23/60 ,  G02B6/13 ,  H01L27/02 ,  H02H9/04 ,  G02B6/122 ,  G02B6/12

    Abstract: An optical integrated circuit device includes an electrically insulating substrate, an optical connection disposed at a boundary of the optical integrated circuit, and a first electrostatic discharge (ESD) protection structure in direct contact with and electrically coupled to the first waveguide. The optical connection includes a first waveguide. The first waveguide is disposed on the electrically insulating substrate and configured to transmit an optical signal. The first ESD protection structure is both electrically non-insulating and substantially optically transparent to the optical signal. An ESD diode including an anode and a cathode is electrically coupled to the first ESD protection structure. A ground connection is electrically coupled to the anode of the ESD diode.

    PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERATION
    8.
    发明申请
    PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERATION 有权

    公开(公告)号：US20250116570A1

    公开(公告)日：2025-04-10

    申请号：US18988238

    申请日：2024-12-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marco Piazza ,  Antonio Canciamilla ,  Piero Orlandi ,  Luca Maggi

    IPC: G01M11/00 ,  G01M11/02 ,  G01R31/317 ,  G01R31/3185 ,  G02B6/293

    Abstract: A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.

    PHOTONIC IC CHIP
    9.
    发明申请
    PHOTONIC IC CHIP 审中-公开

    公开(公告)号：US20200310027A1

    公开(公告)日：2020-10-01

    申请号：US16821370

    申请日：2020-03-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Frédéric Boeuf ,  Luca Maggi

    IPC: G02B6/124 ,  G02B6/34 ,  G02B6/43

    Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

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