公开(公告)号：US20230029946A1

公开(公告)日：2023-02-02

申请号：US17871452

申请日：2022-07-22

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Victor FIORESE ,  Jean-Francois CAILLET ,  Frederic GIANESELLO ,  Fanny LAPORTE

IPC: H01L23/055 ,  H01L23/498 ,  H01L23/66 ,  H01L21/52

Abstract: The present description concerns an electromagnetic wave transmit/receive device comprising a multilayer organic substrate, an integrated circuit chip, flip-chip assembled on the multilayer organic substrate, a package comprising a first cavity, containing the multilayer organic substrate and the integrated circuit chip, and communicating over a channel with a second cavity forming a waveguide for electromagnetic waves.

公开(公告)号：US20240038607A1

公开(公告)日：2024-02-01

申请号：US18226409

申请日：2023-07-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fanny LAPORTE ,  David AUCHERE

IPC: H01L23/13 ,  H01L25/16 ,  H01L23/00 ,  H01L21/306

CPC classification number: H01L23/13 ,  H01L25/165 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L21/306 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15151 ,  H01L2924/16151 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/16235

Abstract: An integrated circuit package includes a cavity within which a circuit device is contained. At least one through hole is provided in at least one wall of the cavity. The at least one through hole includes at least one first portion flaring towards the cavity with a frustoconical shape, for example.

公开(公告)号：US20230223277A1

公开(公告)日：2023-07-13

申请号：US18094775

申请日：2023-01-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fanny LAPORTE ,  Ludovic FOURNEAUD ,  Eric SAUGIER

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48

Abstract: An integrated circuit chip carrier includes a wall surrounding a cavity. The wall includes one or more levels where each level is formed from a layer of a resin around a block. The block is made of a material different from the resin. The block is removed to open the cavity.

公开(公告)号：US20230171927A1

公开(公告)日：2023-06-01

申请号：US17989173

申请日：2022-11-17

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Richard REMBERT ,  Fanny LAPORTE ,  Catherine CADIEUX

IPC: H05K7/20

CPC classification number: H05K7/2039

Abstract: A heat dissipation device includes a substrate with a network of thermally-conductive vias and thermally-conductive layers. The substrate has a first surface and a second surface opposite to the first surface. A heat dissipation interface layer including a stack of a first layer made of a first thermally-conductive material and a second layer made of a second thermally-conductive material. The first material is different from the second material. A surface of the first layer is coplanar with the first surface of the substrate. At least one of the thermally-conductive vias of said network supports and is in contact with the first layer. At least one opening thoroughly crosses the stack of the first and second layers. Material of the substrate fills the opening in the first layer.

公开(公告)号：US20230290712A1

公开(公告)日：2023-09-14

申请号：US18118513

申请日：2023-03-07

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fanny LAPORTE ,  Jerome LOPEZ

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/49827 ,  H01L23/49894 ,  H01L21/4853

Abstract: An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.