公开(公告)号：US07423316B2

公开(公告)日：2008-09-09

申请号：US11596063

申请日：2005-05-12

申请人： Sachiko Kawaji ,  Masayasu Ishiko ,  Takahide Sugiyama ,  Masanori Usui ,  Jun Saito ,  Koji Hotta

发明人： Sachiko Kawaji ,  Masayasu Ishiko ,  Takahide Sugiyama ,  Masanori Usui ,  Jun Saito ,  Koji Hotta

IPC分类号： H01L29/94

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397

摘要： The dense accumulation of hole carriers can be obtained over a wide range of a semiconductor region in a floating state formed within a body region of an IGBT. An n type semiconductor region (52) whose potential is floating is formed within a p− type body region (28). The n type semiconductor region (52) is isolated from an n+ type emitter region (32) and an n− type drift region (26) by the body region (28). Furthermore, a second electrode (62) is formed, so as to oppose to at least a part of the semiconductor region (52) via an insulator film (64). The second electrode (62) does not oppose to the emitter region (32).

摘要翻译： 可以在形成在IGBT的体区内的浮置状态的半导体区域的宽范围内获得空穴载流子的密集堆积。 在p型体区域（28）内形成有浮置电位的n型半导体区域（52）。 n型半导体区域（52）通过身体区域（28）与n + +型发射极区域（32）和n + SUP类型漂移区域（26）隔离 ）。 此外，形成第二电极（62），以经由绝缘膜（64）与半导体区域（52）的至少一部分相对。 第二电极（62）不与发射极区域（32）相对。

公开(公告)号：US20080012040A1

公开(公告)日：2008-01-17

申请号：US11596063

申请日：2005-05-12

申请人： Jun Saito ,  Koji Hotta ,  Sachiko Kawaji ,  Masayasu Ishiko ,  Takahide Sugiyama ,  Masanori Usui

发明人： Jun Saito ,  Koji Hotta ,  Sachiko Kawaji ,  Masayasu Ishiko ,  Takahide Sugiyama ,  Masanori Usui

IPC分类号： H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397

摘要： The dense accumulation of hole carriers can be obtained over a wide range of a semiconductor region in a floating state formed within a body region of an IGBT. An n type semiconductor region (52) whose potential is floating is formed within a p− type body region (28). The n type semiconductor region (52) is isolated from an n+ type emitter region (32) and an n− type drift region (26) by the body region (28). Furthermore, a second electrode (62) is formed, so as to oppose to at least a part of the semiconductor region (52) via an insulator film (64). The second electrode (62) does not oppose to the emitter region (32).

摘要翻译： 可以在形成在IGBT的体区内的浮置状态的半导体区域的宽范围内获得空穴载流子的密集堆积。 在p型体区域（28）内形成有浮置电位的n型半导体区域（52）。 n型半导体区域（52）通过身体区域（28）与n + +型发射极区域（32）和n + SUP类型漂移区域（26）隔离 ）。 此外，形成第二电极（62），以经由绝缘膜（64）与半导体区域（52）的至少一部分相对。 第二电极（62）不与发射极区域（32）相对。

公开(公告)号：US06169299A

公开(公告)日：2001-01-02

申请号：US09258818

申请日：1999-02-26

申请人： Sachiko Kawaji ,  Toshio Murata ,  Masayasu Ishiko ,  Tsutomu Uesugi

发明人： Sachiko Kawaji ,  Toshio Murata ,  Masayasu Ishiko ,  Tsutomu Uesugi

IPC分类号： H01L2974

CPC分类号： H01L29/749 ,  H01L29/0649 ,  H01L29/7455

摘要： The MOS gate thyristor of the present invention has a p+ type anode layer (first semiconductor layer), an n− type base region (second semiconductor layer) with the function of acting as a drift layer, a p− type base region (third semiconductor layer), and an n+ type impurity diffusion layer (fourth semiconductor layer) with the function of acting as a source region. On the surface of the base region, an n+ type floating emitter region (fifth semiconductor layer) is formed, while a first channel region (sixth semiconductor layer) is formed between the impurity diffusion layer and the floating emitter region. At the lower ends of the fourth semiconductor layer and the first channel region an insulation layer is formed. The insulation layer acts to suppress the operation of a parasitic thyristor to ensure a reliable turn-off operation of the transistor. A portion of the semiconductor extends from the n+ type floating emitter region and lies underneath the insulation layer in the direction alongside the principal plane of the p+ type anode layer. The extended semiconductor portion helps broaden the carrier injection path.

摘要翻译： 本发明的MOS栅极晶闸管具有p +型阳极层（第一半导体层），具有作为漂移层的功能的n型基极区域（第二半导体层），p型基极区域（第三半导体层 层）和具有作为源极区域的功能的n +型杂质扩散层（第四半导体层）。 在基极区域的表面上形成n +型浮置发射极区域（第五半导体层），同时在杂质扩散层和浮置发射极区域之间形成第一沟道区域（第六半导体层）。 在第四半导体层的下端和第一沟道区域形成绝缘层。 绝缘层用于抑制寄生晶闸管的操作，以确保晶体管的可靠的关断操作。 半导体的一部分从n +型浮置发射极区域延伸并且位于绝缘层下方沿着p +型阳极层的主平面的方向。 延伸的半导体部分有助于拓宽载流子注入路径。

公开(公告)号：US07569875B2

公开(公告)日：2009-08-04

申请号：US11717790

申请日：2007-03-14

申请人： Takashi Suzuki ,  Sachiko Tanaka ,  Masayasu Ishiko ,  Jun Saito ,  Tsuyoshi Nishiwaki ,  Yukihiro Hisanaga ,  Hidehiro Nakagawa ,  Hirokazu Saito

发明人： Takashi Suzuki ,  Sachiko Tanaka ,  Masayasu Ishiko ,  Jun Saito ,  Tsuyoshi Nishiwaki ,  Yukihiro Hisanaga ,  Hidehiro Nakagawa ,  Hirokazu Saito

IPC分类号： H01L29/80

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66136 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/868

摘要： A semiconductor device having a substrate; an emitter electrode or source electrode formed on the top surface side of the substrate; a gate electrode formed on the top surface side of the substrate; and a collector electrode or drain electrode formed on the bottom surface side of the substrate. The device includes an insulating region formed so as to surround a device-forming region provided on the top surface side of the substrate; and a drift region of the device-forming region, the drift region being in contact with the insulating region, is formed of a semiconductor layer having the same conduction type as that of a channel formed through application of an electric potential to the gate electrode. The gate electrode is a trench gate. An outer peripheral portion of the emitter electrode or source electrode extends in a width of 20 μm or more over the top surface of the insulating region. The insulating region includes, in its interior, a dielectric region having a relative dielectric constant lower than that of the insulating region.

摘要翻译： 一种具有基板的半导体器件; 形成在所述基板的上表面侧的发射电极或源电极; 形成在所述基板的上表面侧的栅电极; 以及形成在基板的底面侧的集电极电极或漏电极。 该器件包括形成为围绕设置在衬底的顶表面侧上的器件形成区域的绝缘区域; 并且与绝缘区域接触的器件形成区域的漂移区域由与通过向栅电极施加电位形成的沟道相同的导电类型的半导体层形成。 栅电极是沟槽栅极。 发射电极或源电极的外周部分在绝缘区域的上表面上延伸20μm以上的宽度。 绝缘区域在其内部包括具有低于绝缘区域的相对介电常数的介电区域。

公开(公告)号：US20070221950A1

公开(公告)日：2007-09-27

申请号：US11717790

申请日：2007-03-14

申请人： Takashi Suzuki ,  Sachiko Tanaka ,  Masayasu Ishiko ,  Jun Saito ,  Tsuyoshi Nishiwaki ,  Yukihiro Hisanaga ,  Hidehiro Nakagawa ,  Hirokazu Saito

发明人： Takashi Suzuki ,  Sachiko Tanaka ,  Masayasu Ishiko ,  Jun Saito ,  Tsuyoshi Nishiwaki ,  Yukihiro Hisanaga ,  Hidehiro Nakagawa ,  Hirokazu Saito

IPC分类号： H01L29/74

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66136 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/868

摘要： A semiconductor device having a substrate; an emitter electrode or source electrode formed on the top surface side of the substrate; a gate electrode formed on the top surface side of the substrate; and a collector electrode or drain electrode formed on the bottom surface side of the substrate. The device includes an insulating region formed so as to surround a device-forming region provided on the top surface side of the substrate; and a drift region of the device-forming region, the drift region being in contact with the insulating region, is formed of a semiconductor layer having the same conduction type as that of a channel formed through application of an electric potential to the gate electrode. The gate electrode is a trench gate. An outer peripheral portion of the emitter electrode or source electrode extends in a width of 20 μm or more over the top surface of the insulating region. The insulating region includes, in its interior, a dielectric region having a relative dielectric constant lower than that of the insulating region.

摘要翻译： 一种具有基板的半导体器件; 形成在所述基板的上表面侧的发射电极或源电极; 形成在所述基板的上表面侧的栅电极; 以及形成在基板的底面侧的集电极电极或漏电极。 该器件包括形成为围绕设置在衬底的顶表面侧上的器件形成区域的绝缘区域; 并且与绝缘区域接触的器件形成区域的漂移区域由与通过向栅电极施加电位形成的沟道相同的导电类型的半导体层形成。 栅电极是沟槽栅极。 发射电极或源电极的外周部分在绝缘区域的上表面上延伸20μm以上的宽度。 绝缘区域在其内部包括具有低于绝缘区域的相对介电常数的介电区域。

公开(公告)号：US20090224353A1

公开(公告)日：2009-09-10

申请号：US12382012

申请日：2009-03-05

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko ,  Hirokazu Fujiwara ,  Masaki Konishi

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko ,  Hirokazu Fujiwara ,  Masaki Konishi

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/417 ,  H01L29/861

摘要： A diode includes the following: an n type semiconductor region; a p type semiconductor region provided in a part of a front face of the n type semiconductor region; an anode electrode (front face electrode) which adjoins a front face of the n type semiconductor region and a front face of the p type semiconductor region while at least forming a Schottky junction on a front face of the n type semiconductor region; and an insulating region which has a right-hand side (first side) and a left-hand side (second side) adjacent to the n type semiconductor region, the right-hand side facing a second n type semiconductor region which is located below the Schottky junction, the left-hand side facing a first n type semiconductor region which is located below a pn junction between the n type semiconductor region and the p type semiconductor region.

摘要翻译： 二极管包括：n型半导体区域; 设置在n型半导体区域的正面的一部分中的p型半导体区域; 邻接n型半导体区域的前表面和p型半导体区域的正面的阳极电极（正面电极），同时至少在n型半导体区域的正面上形成肖特基结; 以及具有与n型半导体区域相邻的右侧（第一侧）和左侧（第二侧）的绝缘区域，所述右侧面向位于所述n型半导体区域下方的第二n型半导体区域 肖特基结，左手侧面对位于n型半导体区域和p型半导体区域之间的pn结的下方的第一n型半导体区域。

公开(公告)号：US07943957B2

公开(公告)日：2011-05-17

申请号：US12097811

申请日：2006-11-17

申请人： Masato Taki ,  Masahiro Kawakami ,  Kiyoharu Hayakawa ,  Masayasu Ishiko

发明人： Masato Taki ,  Masahiro Kawakami ,  Kiyoharu Hayakawa ,  Masayasu Ishiko

IPC分类号： H01L29/861

CPC分类号： H01L29/8611 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/24 ,  H01L29/402 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624

摘要： A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.

摘要翻译： 二极管10包括层叠有半导体衬底20，绝缘体膜30和半导体层40的SOI衬底。在半导体中形成底部半导体区域60，中间半导体区域53和表面半导体区域54 底部半导体区域60包括高浓度的n型杂质。 中间半导体区域53包括低浓度的n型杂质。 表面半导体区域54包括p型杂质。

公开(公告)号：US20090230405A1

公开(公告)日：2009-09-17

申请号：US12382369

申请日：2009-03-13

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.

摘要翻译： 二极管的制造方法包括：在晶体生长方法的N型半导体层上形成P型半导体膜; 在P型半导体膜上形成第一金属膜，使得第一金属膜与欧姆接触的P型半导体膜接触; 在所述第一金属膜上形成具有开口的掩模; 经由所述开口蚀刻所述第一金属膜的一部分和所述P型半导体膜的一部分，使得所述N型半导体层的一部分露出; 并且在N型半导体层的一部分上形成第二金属膜，使得第二金属膜以肖特基接触接触N型半导体层。

公开(公告)号：US20090184370A1

公开(公告)日：2009-07-23

申请号：US12097811

申请日：2006-11-17

申请人： Masato Taki ,  Masahiro Kawakami ,  Kiyoharu Hayakawa ,  Masayasu Ishiko

发明人： Masato Taki ,  Masahiro Kawakami ,  Kiyoharu Hayakawa ,  Masayasu Ishiko

IPC分类号： H01L29/36 ,  H01L21/762

CPC分类号： H01L29/8611 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/24 ,  H01L29/402 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624

摘要： A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.

摘要翻译： 二极管10包括层叠有半导体衬底20，绝缘体膜30和半导体层40的SOI衬底。在半导体中形成底部半导体区域60，中间半导体区域53和表面半导体区域54 底部半导体区域60包括高浓度的n型杂质。 中间半导体区域53包括低浓度的n型杂质。 表面半导体区域54包括p型杂质。

公开(公告)号：US07396735B2

公开(公告)日：2008-07-08

申请号：US10538222

申请日：2003-12-09

申请人： Kazuyuki Nakanishi ,  Tadashi Oshima ,  Hideo Hasegawa ,  Hiroyuki Mori ,  Hideo Tachikawa ,  Yukio Miyachi ,  Yasushi Yamada ,  Hiroyuki Ueda ,  Masayasu Ishiko

发明人： Kazuyuki Nakanishi ,  Tadashi Oshima ,  Hideo Hasegawa ,  Hiroyuki Mori ,  Hideo Tachikawa ,  Yukio Miyachi ,  Yasushi Yamada ,  Hiroyuki Ueda ,  Masayasu Ishiko

IPC分类号： H01L21/76

CPC分类号： H01L23/3732 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor element heat dissipating member is provided which has excellent heat dissipation characteristics and adhesion characteristics and enables production of a semiconductor device at a low cost. A semiconductor device using the same, and a method of producing the same are also provided. The semiconductor element heat dissipating member has a conductive substrate and an electrically insulating amorphous carbon film containing hydrogen, and the electrically insulating amorphous carbon film is formed at least on a region of the conductive substrate on which region a semiconductor element is to be mounted.

摘要翻译： 提供了具有优异的散热特性和粘合特性的半导体元件散热构件，并且能够以低成本制造半导体器件。 还提供了使用该半导体器件的半导体器件及其制造方法。 半导体元件散热构件具有导电基板和含有氢的电绝缘非晶碳膜，并且至少在导电基板的要安装半导体元件的区域的区域上形成电绝缘非晶碳膜。