公开(公告)号：US06544461B1

公开(公告)日：2003-04-08

申请号：US09677555

申请日：2000-10-02

申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

IPC分类号： B29C4502

CPC分类号： G01R1/0483

摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。 可以在模制步骤期间使用垫圈来保护互连触点。

公开(公告)号：US06208157B1

公开(公告)日：2001-03-27

申请号：US09298769

申请日：1999-04-23

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  G01R1/0433 ,  G01R1/0483

摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

公开(公告)号：US06642730B1

公开(公告)日：2003-11-04

申请号：US10351767

申请日：2003-01-27

申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

IPC分类号： G01R3102

CPC分类号： G01R1/0483

摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

公开(公告)号：US06353326B2

公开(公告)日：2002-03-05

申请号：US09143300

申请日：1998-08-28

申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

IPC分类号： G01R3102

CPC分类号： G01R1/0483

摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。

公开(公告)号：US06396291B1

公开(公告)日：2002-05-28

申请号：US09723101

申请日：2000-11-28

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  G01R1/0483

摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

公开(公告)号：US6072326A

公开(公告)日：2000-06-06

申请号：US916434

申请日：1997-08-22

申请人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

发明人： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth ,  Derek Gochnour ,  Alan G. Wood ,  John O. Jacobson

IPC分类号： G01R1/04 ,  G01R31/02

CPC分类号： G01R1/0466 ,  G01R1/0433 ,  G01R1/0483

摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.

摘要翻译： 提供了一种用于测试半导体部件的系统和方法。 该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。 载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。 此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。 插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。 在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。 然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

公开(公告)号：US5893726A

公开(公告)日：1999-04-13

申请号：US990866

申请日：1997-12-15

申请人： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

发明人： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

IPC分类号： H01L23/04 ,  H01L23/10 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/10 ,  H01L23/04 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195

摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.

摘要翻译： 半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。 盖可以用模制塑料或冲压金属预制，并使用固化的密封件​​附接到基底。 还可以通过基底提供孔，以在形成密封期间允许压力平衡。 盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。 在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

公开(公告)号：US06313651B1

公开(公告)日：2001-11-06

申请号：US09322724

申请日：1999-05-28

申请人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

发明人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

IPC分类号： G01R3102

CPC分类号： G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

摘要翻译： 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

公开(公告)号：US6057597A

公开(公告)日：2000-05-02

申请号：US172451

申请日：1998-10-14

申请人： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

发明人： Warren M. Farnworth ,  David R. Hembree ,  Derek Gochnour ,  Salman Akram ,  John O. Jacobson ,  James M. Wark ,  Steven G. Thummel

IPC分类号： H01L23/04 ,  H01L23/10 ,  H01L23/12

CPC分类号： H01L23/10 ,  H01L23/04 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195

摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.

摘要翻译： 半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。 盖可以用模制塑料或冲压金属预制，并使用固化的密封件​​附接到基底。 还可以通过基底提供孔，以在形成密封期间允许压力平衡。 盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。 在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

公开(公告)号：US6040702A

公开(公告)日：2000-03-21

申请号：US888075

申请日：1997-07-03

申请人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

发明人： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  G01R31/02 ,  H01L21/66 ,  H01L23/12 ,  H01L23/32 ,  H01R13/631 ,  H01R13/642 ,  H01R33/76

CPC分类号： G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701

摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

摘要翻译： 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。