公开(公告)号：US20050048709A1

公开(公告)日：2005-03-03

申请号：US10684713

申请日：2003-10-14

申请人： Paul Layman ,  John McMacken ,  J. Thomson ,  Samir Chaudhry ,  Jack Zhao

发明人： Paul Layman ,  John McMacken ,  J. Thomson ,  Samir Chaudhry ,  Jack Zhao

IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/7827 ,  Y10S438/981

摘要： An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions. In an associated method of manufacturing the semiconductor device, a first and second source/drain regions are formed in a semiconductor layer. A first field-effect transistor gate region, including a channel and a gate electrode is formed over the first source drain region and a second field-effect transistor gate region is formed over the second source/drain region. Fifth and sixth source/drain regions are then formed for each of the first and second field-effect transistors and further having the appropriate conductivity type. Variable thickness gate oxides are created by appropriately masking, etching, and regrowing gate oxides. As a result, the formed transistors operate at different operating voltages. Thus a plurality of such transistors operating at different operating voltage (as a function of the gate oxide thickness) can be formed in an integrated circuit.

摘要翻译： 用于创建多个工作电压MOSFET的架构。 通常，集成电路结构包括具有沿着平面形成的主表面的半导体区域和形成在表面中的第一和第二间隔开的掺杂区域。 形成与第一区域不同的导电类型的沟道的第三掺杂区域位于第一区域上方。 具有不同导电性并形成沟道的第四掺杂区位于第二区上方。 为两个晶体管中的每个晶体管产生栅极结构的过程允许在两个晶体管之间形成不同厚度的氧化物层。 因此，晶体管能够在不同的工作电压（包括不同的阈值电压）下工作。 每个晶体管还包括分别位于第三和第四区域上的第五和第六层，并且相对于第三和第四区域具有相反的导电类型。 在制造半导体器件的相关方法中，在半导体层中形成第一和第二源/漏区。 在第一源极漏极区域上形成包括沟道和栅电极的第一场效应晶体管栅极区域，并且在第二源极/漏极区域上形成第二场效应晶体管栅极区域。 然后为第一和第二场效应晶体管中的每一个形成第五和第六源极/漏极区域，并且还具有适当的导电类型。 通过适当地掩蔽，蚀刻和再生栅极氧化物来产生可变厚度的栅极氧化物。 结果，形成的晶体管在不同的工作电压下工作。 因此，可以在集成电路中形成以不同工作电压（与栅极氧化物厚度的函数））工作的多个这样的晶体管。

公开(公告)号：US20070238243A1

公开(公告)日：2007-10-11

申请号：US11809873

申请日：2007-06-01

申请人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  J. Thomson ,  Jack Zhao

发明人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  J. Thomson ,  Jack Zhao

IPC分类号： H01L21/765

CPC分类号： H01L29/66666 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.

摘要翻译： 与集成电路中使用的垂直MOSFET器件和电容器相关的工艺和架构。 通常，集成电路结构包括具有沿其平面形成的主表面的半导体层，并且还包括形成在表面中的第一掺杂区域。 与第一掺杂区域不同的导电类型的第二掺杂区域位于第一区域上方。 与第二区域不同的导电类型的第三掺杂区域位于第二区域上方。 在本发明的一个实施例中，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。 在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。 集成电路还包括具有底板，电介质层和顶部电容器板的电容器。 在相关联的制造方法中，在半导体层上形成从由场效应晶体管的源极区域和漏极区域中选择的第一器件区域。 第一场效应晶体管栅极区域形成在第一器件区域上。 在半导体层上还形成有包括设置在其间的介电层的顶层和底层的电容器。 在另一个实施例中，电容器层形成在形成在半导体层中的沟槽或窗口内。

公开(公告)号：US20070111414A1

公开(公告)日：2007-05-17

申请号：US11419356

申请日：2006-05-19

申请人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  J. Thomson ,  Jack Zhao

发明人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  J. Thomson ,  Jack Zhao

IPC分类号： H01L21/337

CPC分类号： H01L29/42392 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a relatively thin vertical layer of single crystalline material. A MOSFET gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel, the regions being appropriately doped to effect MOSFET action.

摘要翻译： 一种用于创建垂直绝缘体上硅的MOSFET的架构。 通常，集成电路结构包括具有沿着平面形成的主表面的半导体区域和形成在表面中的第一源极/漏极接触区域。 相对薄的单晶层在主表面上垂直取向，并且包括第一源极/漏极掺杂区域，在该第一源极/漏极掺杂区域上定位有掺杂沟道区，其上定位有第二源极/漏极区。 邻近所述第一和第二源极/漏极区域和所述沟道区域设置绝缘层，用作SOI器件的绝缘材料。 在另一个实施例中，绝缘材料仅与所述第一和所述第二源极/漏极区相邻。 导电区域与通道区域相邻，用于将沟道区域的背面连接到地，例如以防止沟道区域浮动。 在制造半导体器件的相关方法中，第一源极/漏极区形成在相对薄的单晶材料垂直层中。 在第一源极/漏极区域上形成包括沟道和栅电极的MOSFET栅极区域。 然后在该通道上形成第二源极/漏极区域，该区域被适当地掺杂以实现MOSFET的动作。

公开(公告)号：US20070228440A1

公开(公告)日：2007-10-04

申请号：US11809686

申请日：2007-05-31

申请人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  J. Thomson ,  Jack Zhao

发明人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  J. Thomson ,  Jack Zhao

IPC分类号： H01L29/94

CPC分类号： H01L29/66666 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.

公开(公告)号：US20060166429A1

公开(公告)日：2006-07-27

申请号：US11390015

申请日：2006-03-27

申请人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  Ross Thomson ,  Jack Zhao

发明人： Samir Chaudhry ,  Paul Layman ,  John McMacken ,  Ross Thomson ,  Jack Zhao

IPC分类号： H01L21/8238 ,  H01L21/337 ,  H01L21/336

CPC分类号： H01L29/66909 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/098 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/8083

摘要： An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

公开(公告)号：US20050170554A1

公开(公告)日：2005-08-04

申请号：US10513121

申请日：2003-05-07

申请人： Michelle Griglione ,  Paul Layman ,  Mohamed Laradji ,  J. Thomson ,  Samir Chaudhry

发明人： Michelle Griglione ,  Paul Layman ,  Mohamed Laradji ,  J. Thomson ,  Samir Chaudhry

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L29/12 ,  H01L21/00 ,  H01L21/16

CPC分类号： B82Y10/00 ,  H01L27/08 ,  H01L28/10 ,  H01L29/127

摘要： A thin-film multilayer high-Q inductor having a ferromagnetic core and spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical connection with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The first metal runners and second metal runners are oriented such that one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias., forming a continuously conductive structure having a generally helical shape. An inductor core is formed by first forming a silicon layer between each one of the plurality of first metal runners. A germanium layer is formed thereover and the structure is annealed, causing formation of quantum dots of germanium. A cobalt layer is then formed over the quantum dots and another anneal process drives the cobalt into the quantum dots, where it is captured to form the ferromagnetic core.

摘要翻译： 通过在半导体衬底上形成多个平行的第一金属流道，形成具有铁磁芯并跨越至少三个金属层的薄膜多层高Q电感器。 多个第一和第二垂直导电通孔形成为与多个金属流道的每个端部电连接。 在多个第一和第二导电通孔之上形成多个第三和第四导电通孔，并且形成互连多个第三和第四导电通孔的多个第二金属流道。 第一金属流道和第二金属流道被定向成使得第一金属流道的一端通过第一和第三垂直导电通孔连接到第二金属流道的上覆端。 第二金属流道的另一端通过第二和第四垂直导电通孔连接到下一个金属一个流道，形成具有大致螺旋形状的连续导电结构。 通过首先在多个第一金属流道中的每一个之间形成硅层来形成电感器芯。 在其上形成锗层，结构退火，形成锗量子点。 然后在量子点上形成钴层，另一个退火工艺将钴驱动到量子点中，在其中被捕获以形成铁磁芯。

公开(公告)号：US07151059B2

公开(公告)日：2006-12-19

申请号：US10762788

申请日：2004-01-22

申请人： Samir Chaudhry ,  Sidhartha Sen ,  Sundar Srinivasan Chetlur ,  Richard William Gregor ,  Pradip Kumar Roy

发明人： Samir Chaudhry ,  Sidhartha Sen ,  Sundar Srinivasan Chetlur ,  Richard William Gregor ,  Pradip Kumar Roy

IPC分类号： H01L21/31

CPC分类号： H01L21/28194 ,  C30B29/06 ,  C30B33/005 ,  H01L21/02238 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/513 ,  H01L29/517

摘要： A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

摘要翻译： 公开了减小的特征尺寸MOS晶体管及其制造方法。 本发明减少短信道效应，但不包括LDD结构。在说明性实施例中，MOS晶体管的栅极长度为1.25μm或更小。 示例性MOS晶体管包括与衬底形成平面且基本上无应力的界面的栅极氧化物。 由于氧化物/衬底界面的平坦性和基本无应力的性质，热载流子的发生率以及有害的热载流子效应降低。 通过消除LDD结构的使用，制造复杂度降低，串联源极 - 漏极电阻降低，从而提高驱动电流和开关速度。

公开(公告)号：US06828561B2

公开(公告)日：2004-12-07

申请号：US10260694

申请日：2002-09-30

申请人： Paul Arthur Layman ,  Samir Chaudhry ,  James Gary Norman ,  J. Ross Thomson

发明人： Paul Arthur Layman ,  Samir Chaudhry ,  James Gary Norman ,  J. Ross Thomson

IPC分类号： H01L2978

CPC分类号： G01T1/245

摘要： A memory array operates as an alpha particle detector. A predetermined state is stored in each memory storage location. The operating voltage of the memory array is established at a voltage where the stored values are relatively stable and not subject to change except as a result of alpha particle impingement. Impinging alpha particles are detected by the state changes they cause in the memory storage locations.

摘要翻译： 存储器阵列用作α粒子检测器。 预定状态存储在每个存储器存储位置。 存储器阵列的工作电压建立在电压下，其中存储的值相对稳定并且不会改变，除非是由α粒子撞击造成的。 通过它们在存储器存储位置中引起的状态改变来检测入射α粒子。

公开(公告)号：US06738294B2

公开(公告)日：2004-05-18

申请号：US10262654

申请日：2002-09-30

申请人： Paul Arthur Layman ,  Samir Chaudhry ,  James Gary Norman ,  J. Ross Thomson

发明人： Paul Arthur Layman ,  Samir Chaudhry ,  James Gary Norman ,  J. Ross Thomson

IPC分类号： G11C700

CPC分类号： G11C5/00 ,  H01L2223/5444

摘要： A method of identifying an integrated circuit device based on the initial state of certain memory cells within a memory array of the integrated circuit device. For many cells in the memory array the initial state is relatively consistent at each power-up, due to mismatches between the transistors that form each memory cell. Thus these consistent initial states provide a signature of the memory array and the integrated circuit device.

摘要翻译： 基于集成电路器件的存储器阵列内的某些存储器单元的初始状态来识别集成电路器件的方法。 对于存储器阵列中的许多单元，由于形成每个存储单元的晶体管之间的失配，初始状态在每次上电时相对一致。 因此，这些一致的初始状态提供了存储器阵列和集成电路器件的签名。

公开(公告)号：US07491610B2

公开(公告)日：2009-02-17

申请号：US11809873

申请日：2007-06-01

申请人： Samir Chaudhry ,  Paul Arthur Layman ,  John Russell McMacken ,  J. Ross Thomson ,  Jack Qingsheng Zhao

发明人： Samir Chaudhry ,  Paul Arthur Layman ,  John Russell McMacken ,  J. Ross Thomson ,  Jack Qingsheng Zhao

IPC分类号： H01L21/8232

CPC分类号： H01L29/66666 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region. is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.

摘要翻译： 与集成电路中使用的垂直MOSFET器件和电容器相关的工艺和架构。 集成电路结构包括具有主表面的半导体层，并且还包括形成在表面中的第一掺杂区域。 与第一掺杂区域不同的导电类型的第二掺杂区域位于第一区域上方。 与第二区域不同的导电类型的第三掺杂区域位于第二区域上方。 集成电路包括具有底板，电介质层和顶板的电容器。 在相关的制造方法中，第一装置区域。 形成在半导体层上。 在第一器件区域上形成场效应晶体管栅极区域。 在半导体层上形成包括顶层和底层的电容器和电介质层。