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公开(公告)号：US11751433B2
公开(公告)日：2023-09-05
申请号：US17225174
申请日：2021-04-08
Applicant: Samsung Display Co., Ltd.
Inventor： Hyuk Soon Kwon
IPC: H10K59/121 , H01L27/12 , H10K59/131 , H10K71/00
CPC classification number: H10K59/1213 , H01L27/1214 , H10K59/131 , H10K71/00
Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.
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公开(公告)号：US09368518B2
公开(公告)日：2016-06-14
申请号：US14303794
申请日：2014-06-13
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Doo Youl Lee , Se Myung Kwon , Hyuk Soon Kwon , Jang Soo Kim , Hyung Min Kim , Jin-Ho Oh
IPC: H01L27/12 , H01L29/417 , H01L21/02 , H01L21/768 , H01L29/786 , H01L21/3213
CPC classification number: H01L27/124 , H01L21/02164 , H01L21/02565 , H01L21/32139 , H01L21/76852 , H01L27/1225 , H01L27/1288 , H01L29/41733 , H01L29/45 , H01L29/66969 , H01L29/78606 , H01L29/7869
Abstract: A thin film transistor array panel includes: a gate conductor disposed on a substrate and including a gate line and a gate electrode, a semiconductor layer overlapping the gate electrode and including an oxide semiconductor, a data conductor including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, a sidewall covering side surface parts of the drain electrode and the source electrode adjacent to a channel region of the semiconductor layer, and a passivation layer covering the source electrode, the drain electrode, and the sidewall.
Abstract translation: 薄膜晶体管阵列面板包括：栅极导体，其设置在基板上，包括栅极线和栅电极，与栅电极重叠并包括氧化物半导体的半导体层，数据导体，包括与栅极线相交的数据线， 连接到数据线的源电极和面对源电极的漏电极，覆盖与半导体层的沟道区相邻的漏电极和源电极的侧表面部分的侧壁以及覆盖源电极的钝化层 ，漏电极和侧壁。
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3.再颁专利公开(公告)号：USRE49814E1
公开(公告)日：2024-01-23
申请号：US17218472
申请日：2021-03-31
Applicant: Samsung Display Co., Ltd.
Inventor： Hyuk Soon Kwon
IPC: H01L27/12 , G02F1/1362 , H01L29/786 , H10K59/121 , G02F1/1343 , G02F1/1368
CPC classification number: H01L27/1288 , G02F1/13624 , G02F1/136209 , H01L27/1225 , H01L27/1248 , H01L27/1251 , H01L27/1255 , H01L29/7869 , H01L29/78606 , H01L29/78633 , G02F1/1368 , G02F1/13439 , G02F1/136231 , G02F2201/123 , H10K59/1213
Abstract: A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.
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4.发明授权公开(公告)号：US10446591B2
公开(公告)日：2019-10-15
申请号：US15452602
申请日：2017-03-07
Applicant: Samsung Display Co., Ltd.
Inventor： Hyuk Soon Kwon
IPC: H01L27/12 , H01L29/786 , H01L27/32 , G02F1/1362 , G02F1/1343 , G02F1/1368
Abstract: A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.
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公开(公告)号：US10483340B2
公开(公告)日：2019-11-19
申请号：US15481273
申请日：2017-04-06
Applicant: Samsung Display Co., Ltd.
Inventor： Hyuk Soon Kwon
Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.
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Patent Agency Ranking
公开(公告)号：US09698167B2
公开(公告)日：2017-07-04
申请号：US14534508
申请日：2014-11-06
Applicant: Samsung Display Co., Ltd.
Inventor： Doo Youl Lee , Hyuk Soon Kwon , Jang Soo Kim
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1225 , H01L27/1233 , H01L27/127 , H01L27/1288
Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.
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7.发明授权Crystallization method of thin film transistor, thin film transistor array panel and manufacturing method for thin film transistor array panel 有权薄膜晶体管，薄膜晶体管阵列面板的结晶方法及薄膜晶体管阵列面板的制造方法公开(公告)号：US09406807B2
公开(公告)日：2016-08-02
申请号：US14290788
申请日：2014-05-29
Applicant: Samsung Display Co., Ltd.
Inventor： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
IPC: H01L29/786 , H01L27/12
CPC classification number: H01L29/78663 , H01L27/1222 , H01L27/1285
Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
Abstract translation: 本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。 本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。 结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。
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公开(公告)号：US10991784B2
公开(公告)日：2021-04-27
申请号：US16686033
申请日：2019-11-15
Applicant: Samsung Display Co., Ltd.
Inventor： Hyuk Soon Kwon
Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.
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公开(公告)号：US10886470B2
公开(公告)日：2021-01-05
申请号：US15483879
申请日：2017-04-10
Applicant: Samsung Display Co. Ltd.
Inventor： Hyuk Soon Kwon , Chun Gi You , Sun Park , Jong Moo Huh
Abstract: An organic light emitting display device includes a substrate, a semiconductor pattern disposed on the substrate, a conductive line disposed in a different layer from the semiconductor pattern, a pixel electrode disposed on the conductive line and on the semiconductor pattern, and a connection electrode disposed in a same layer as the pixel electrode. The connection electrode may be connected to the semiconductor pattern and the conductive line.
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公开(公告)号：US20160020230A1
公开(公告)日：2016-01-21
申请号：US14534508
申请日：2014-11-06
Applicant: Samsung Display Co., Ltd.
Inventor： Doo Youl Lee , Hyuk Soon Kwon , Jang Soo Kim
IPC: H01L27/12
CPC classification number: H01L27/1225 , H01L27/1233 , H01L27/127 , H01L27/1288
Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.
Abstract translation: 公开了一种薄膜晶体管阵列面板，其包括：包括显示区域和周边区域的基板; 设置在所述基板上的第二半导体层，并且设置在布置在所述显示区域和所述周边区域中的第一半导体层上; 以及设置在所述第一半导体层和所述第二半导体层上的钝化层，其中所述第一半导体层和所述第二半导体层包括氧化物半导体，并且所述第一半导体层的厚度与所述第二半导体层的厚度不同。
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