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1.发明申请METHOD FOR REMOVING SEED LAYER IN MANUFACTURING PRINTED CIRCUIT BOARD AND PRINTED CIRCUIT BOARD MANUFACTURED BY USING THE SAME 有权用于在制造印刷电路板中移除所述层的方法和使用其制造的印刷电路板公开(公告)号：US20140076619A1
公开(公告)日：2014-03-20
申请号：US13826857
申请日：2013-03-14
发明人： Sung Han , Yoon Su Kim , Kyoung Moo Harr , Kyung Seob Oh , Kyung Suk Shim , Du Sung Jung
CPC分类号： H05K3/06 , H05K1/02 , H05K3/027 , H05K3/108 , H05K2203/087 , H05K2203/107 , Y10T29/49156
摘要： Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.
摘要翻译： 本发明公开了一种在制造印刷电路板中去除种子层的方法，该方法包括：在印刷电路板上形成光刻胶层，该印刷电路板上形成有种子层; 根据预定图案去除光致抗蚀剂层; 在除去光致抗蚀剂层的预定图案上形成用于电路的镀层; 通过除去镀层周围的光致抗蚀剂层来曝光晶种层; 通过在填充有预定气体的反应器中进行种子层暴露的基板的化学反应，在种子层和镀层的表面上形成腐蚀层; 以及通过在腐蚀层上照射激光以除去腐蚀层来去除种子层。
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公开(公告)号：US10224288B2
公开(公告)日：2019-03-05
申请号：US15728064
申请日：2017-10-09
发明人： Kyung Seob Oh , Kyoung Moo Harr , Doo Hwan Lee , Seung Chul Oh , Hyoung Joon Kim , Yoon Suk Cho
IPC分类号： H01L23/31 , H01L23/538 , H01L23/498
摘要： A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.
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公开(公告)号：US10170382B2
公开(公告)日：2019-01-01
申请号：US15633478
申请日：2017-06-26
发明人： Hyoung Joon Kim , Kyung Seob Oh , Kyoung Moo Harr
IPC分类号： H01L23/28 , H01L23/053 , H01L23/24 , H01L23/00
摘要： A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.
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公开(公告)号：US10211149B2
公开(公告)日：2019-02-19
申请号：US15710374
申请日：2017-09-20
发明人： Kyoung Moo Harr , Kyung Seob Oh , Hyoung Joon Kim
IPC分类号： H01L23/528 , H01L23/522 , H01L23/31 , H01L23/00
摘要： A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.
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公开(公告)号：US10043758B1
公开(公告)日：2018-08-07
申请号：US15689659
申请日：2017-08-29
发明人： Ji Hyun Lee , Hyoung Joon Kim , Kyoung Moo Harr
IPC分类号： H01L23/495 , H01L23/538 , H01L23/00 , H01L23/31
摘要： A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip. The connection member includes a plurality of insulating layers, a plurality of redistribution layers disposed on the plurality of insulating layers, respectively, and a plurality of via layers penetrating through the plurality of insulating layers, respectively, and at least two of the plurality of insulating layers or at least two of the plurality of via layers have different thicknesses.
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公开(公告)号：US09881873B2
公开(公告)日：2018-01-30
申请号：US15420558
申请日：2017-01-31
发明人： Kyung Seob Oh , Kyoung Moo Harr , Doo Hwan Lee , Seung Chul Oh , Hyoung Joon Kim , Yoon Suk Cho
IPC分类号： H01L23/31 , H01L23/538
CPC分类号： H01L23/5389 , H01L23/3114 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2924/18162 , H01L2924/3511
摘要： A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.
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公开(公告)号：US10062652B2
公开(公告)日：2018-08-28
申请号：US15352100
申请日：2016-11-15
发明人： Ji Hyun Lee , Kyoung Moo Harr , Seung Yeop Kook , Ji Hoon Kim , Young Gwan Ko
IPC分类号： H01L23/538 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L21/568 , H01L23/3135 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2924/18162 , H01L2924/3025 , H01L2924/3511
摘要： The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.
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公开(公告)号：US09905526B2
公开(公告)日：2018-02-27
申请号：US15192634
申请日：2016-06-24
发明人： Kyoung Moo Harr , Ji Hoon Kim , Kyung Seob Oh , Sun Ho Kim
CPC分类号： H01L24/16 , H01L23/3128 , H01L23/3677 , H01L23/481 , H01L23/49827 , H01L23/552 , H01L24/19 , H01L24/20 , H01L29/0657 , H01L2224/04105 , H01L2224/12105 , H01L2924/3025 , H01L2924/3512
摘要： An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.
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9.发明授权公开(公告)号：US08957319B2
公开(公告)日：2015-02-17
申请号：US13826857
申请日：2013-03-14
发明人： Sung Han , Yoon Su Kim , Kyoung Moo Harr , Kyung Seob Oh , Kyung Suk Shim , Du Sung Jung
CPC分类号： H05K3/06 , H05K1/02 , H05K3/027 , H05K3/108 , H05K2203/087 , H05K2203/107 , Y10T29/49156
摘要： Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.
摘要翻译： 本发明公开了一种在制造印刷电路板中去除种子层的方法，该方法包括：在印刷电路板上形成光刻胶层，该印刷电路板上形成有种子层; 根据预定图案去除光致抗蚀剂层; 在除去光致抗蚀剂层的预定图案上形成用于电路的镀层; 通过除去镀层周围的光致抗蚀剂层来曝光晶种层; 通过在填充有预定气体的反应器中进行种子层暴露的基板的化学反应，在种子层和镀层的表面上形成腐蚀层; 以及通过在腐蚀层上照射激光以除去腐蚀层来去除种子层。
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10.发明申请PRINTED CIRCUIT BOARD HAVING COPPER PLATED LAYER WITH ROUGHNESS AND METHOD OF MANUFACTURING THE SAME 审中-公开具有粗糙度的铜层的印刷电路板及其制造方法公开(公告)号：US20140186651A1
公开(公告)日：2014-07-03
申请号：US14140392
申请日：2013-12-24
发明人： Sung Han , Yoon Su Kim , Doo Sung Jung , Eun Jung Lim , Kyoung Moo Harr , Kyung Suk Shim , Kyung Seob Oh
CPC分类号： H05K3/385 , H05K2203/095 , H05K2203/122 , Y10T428/12472 , Y10T428/12646
摘要： Disclosed herein are a printed circuit board having a copper plated layer with an anchor shaped surface and roughness by forming the copper plated layer having an anisotropic crystalline orientation structure using a plating inhibitor at the time of forming the copper plated layer serving as a circuit wiring and using composite gas plasma and a dilute acid solution, and a method of manufacturing the same.
摘要翻译： 本发明公开了一种印刷电路板，其具有通过在形成作为电路布线的镀铜层时使用电镀抑制剂的具有各向异性结晶取向结构的铜镀层，具有锚定形状的表面和粗糙度的铜镀层， 使用复合气体等离子体和稀酸溶液及其制造方法。
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