公开(公告)号：US10283204B2

公开(公告)日：2019-05-07

申请号：US15607551

申请日：2017-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Min Choi ,  Dong-Chan Kim ,  Ae-Jeong Lee ,  Moo-Rym Choi

IPC: G06F12/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/22 ,  G11C16/34

Abstract: In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.

公开(公告)号：US08942042B2

公开(公告)日：2015-01-27

申请号：US13772868

申请日：2013-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Jeong Lee ,  Bongyong Lee ,  Dongchan Kim ,  Jaesung Sim

IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3409 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.

Abstract translation: 一种在非易失性存储器件中调整接地选择晶体管的阈值电压的方法包括：在读取操作中向第一接地选择晶体管的栅极提供第一电压，并向第二接地选择晶体管的栅极提供第二电压， 读操作。 非易失性存储器件包括至少一个串，串具有串选择晶体管，存储单元以及串联连接并堆叠在基板上的第一和第二接地选择晶体管。

公开(公告)号：US20140349453A1

公开(公告)日：2014-11-27

申请号：US14455429

申请日：2014-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong Lee ,  Sang-Hoon Kim ,  Ae-Jeong Lee ,  Dongchan Kim

IPC: H01L27/115

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

Abstract translation: 存储器件包括在衬底上平行延伸的多个细长栅极叠层和设置在相邻栅极叠层之间沟槽中的至少一个绝缘区域。 所述至少一个绝缘区具有具有第一宽度的线性第一部分和具有大于第一宽度的第二宽度的加宽的第二部分。 公共源极区域设置在至少一个绝缘区域下方的衬底中。 这些器件还包括各自的导电插塞，其穿过至少一个绝缘区域的加宽的第二部分中的相应导电插塞并且电连接到公共源极区域，以及设置在相邻栅极叠层之间的导电插塞上的至少一个捆扎线 并与导电插头直接接触。