公开(公告)号：US08942042B2

公开(公告)日：2015-01-27

申请号：US13772868

申请日：2013-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Jeong Lee ,  Bongyong Lee ,  Dongchan Kim ,  Jaesung Sim

IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3409 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.

Abstract translation: 一种在非易失性存储器件中调整接地选择晶体管的阈值电压的方法包括：在读取操作中向第一接地选择晶体管的栅极提供第一电压，并向第二接地选择晶体管的栅极提供第二电压， 读操作。 非易失性存储器件包括至少一个串，串具有串选择晶体管，存储单元以及串联连接并堆叠在基板上的第一和第二接地选择晶体管。

公开(公告)号：US10032787B2

公开(公告)日：2018-07-24

申请号：US15652411

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoocheol Shin ,  Hongsoo Kim ,  Jaesung Sim

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11531 ,  H01L27/105

Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

公开(公告)号：US09515087B2

公开(公告)日：2016-12-06

申请号：US14878453

申请日：2015-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: G11C5/02 ,  H01L27/115 ,  G11C16/30 ,  H01L29/34 ,  G11C16/04

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

Abstract translation: 一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块 逻辑结构。 存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及穿透 堆叠结构并连接到半导体层。

公开(公告)号：US09042175B2

公开(公告)日：2015-05-26

申请号：US13753677

申请日：2013-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesung Sim ,  Bongyong Lee

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/06 ,  G11C7/04 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C2216/14

Abstract: Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.

Abstract translation: 公开了一种非易失性存储器件，其包括连接到位线和字线的存储单元; 电位连接到位线并感测存储在存储单元中的数据的页缓冲器; 以及控制逻辑控制页缓冲器，以在读操作期间根据当前温度来改变位线或连接到位线的感测节点的显影时间。

公开(公告)号：US10332902B2

公开(公告)日：2019-06-25

申请号：US15805513

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  G11C16/30 ,  H01L27/11551

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US09865685B2

公开(公告)日：2018-01-09

申请号：US15403440

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesung Sim ,  Youngwoo Park

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/267 ,  H01L29/161 ,  H01L29/165 ,  H01L29/788 ,  H01L29/16

CPC classification number: H04L49/70 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7883 ,  H04L45/16 ,  H04L49/201 ,  H04L49/3009

Abstract: Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

公开(公告)号：US08953382B2

公开(公告)日：2015-02-10

申请号：US14164586

申请日：2014-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesung Sim ,  Jungdal Choi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/14

CPC classification number: G11C16/344 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/3418

Abstract: Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

Abstract translation: 集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。 提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。 擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

公开(公告)号：US09847341B2

公开(公告)日：2017-12-19

申请号：US14519713

申请日：2014-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoocheol Shin ,  Hongsoo Kim ,  Jaesung Sim

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/105

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

公开(公告)号：US09837429B2

公开(公告)日：2017-12-05

申请号：US15348009

申请日：2016-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/30 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11551

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.