公开(公告)号：USRE49525E1

公开(公告)日：2023-05-09

申请号：US16986448

申请日：2020-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Il Bae ,  Bomsoo Kim ,  Yong-Min Cho

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45 ,  H01L21/308 ,  H01L29/775 ,  B82Y10/00 ,  H01L27/11 ,  H01L29/165

CPC classification number: H01L29/6656 ,  B82Y10/00 ,  H01L21/308 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/78696 ,  H01L27/1104 ,  H01L29/165

Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.

公开(公告)号：US09525036B2

公开(公告)日：2016-12-20

申请号：US14662697

申请日：2015-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il Bae ,  Bomsoo Kim ,  Yong-Min Cho

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L29/08 ,  H01L21/308

CPC classification number: H01L29/41791 ,  H01L21/308 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.

Abstract translation: 提供半导体器件。 翅片设置在基板上，沿长度方向延伸。 第一凹部设置在翅片的侧壁上，使得翅片和第一凹部沿着长度方向布置成直线。 栅极结构在与长度方向交叉的第一方向上跨越翅片。 间隔件设置在门结构的人行道上。 源极/漏极区域设置在第一凹部中。 源极/漏极区形成在间隔物下方。 硅化物层设置在源极/漏极区域上。 硅化物层和源/漏区填充第一凹槽。

公开(公告)号：US09653551B2

公开(公告)日：2017-05-16

申请号：US14980134

申请日：2015-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changwoo Oh ,  Myung Gil Kang ,  Bomsoo Kim ,  Jongshik Yoon

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/1041 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fin portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.