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    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells
    1.
    发明授权
    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells 有权
    包括接地选择晶体管和第一和第二虚拟存储器单元的非易失性存储器件的操作方法

    公开(公告)号：US09548123B2

    公开(公告)日：2017-01-17

    申请号：US14820703

    申请日：2015-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byeong-In Choe ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim ,  Woonkyung Lee

    IPC: G11C16/00 ,  G11C7/00 ,  H01L29/00 ,  H01L27/11 ,  G11C16/14 ,  G11C7/14 ,  G11C16/04 ,  G11C16/30 ,  H01L29/792 ,  H01L27/115 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/14 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    Abstract: A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

    Abstract translation: 非易失性存储器件包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。 所述方法可以包括将字线擦除电压施加到连接到所述单元串的存储单元的字线; 连接到单元串的地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

    Flash Memory Device and Operating Method for Concurrently Applying Different Bias Voltages to Dummy Memory Cells and Regular Memory Cells During Erasure
    2.
    发明申请
    Flash Memory Device and Operating Method for Concurrently Applying Different Bias Voltages to Dummy Memory Cells and Regular Memory Cells During Erasure 有权
    闪存器件和操作方法，用于在擦除期间将不同的偏置电压应用于虚拟存储器单元和常规存储器单元

    公开(公告)号：US20130100735A1

    公开(公告)日：2013-04-25

    申请号：US13680812

    申请日：2012-11-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byeong-In Choe

    IPC: G11C16/06

    CPC classification number: G11C16/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30

    Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

    Abstract translation: 诸如NAND闪存器件的集成电路闪存器件包括常规闪存单元阵列，虚拟闪存单元阵列和擦除控制器。 擦除控制器被配置为在集成电路快闪存储器件的擦除操作期间同时向虚拟闪存单元施加不同于常规闪存单元的预定偏置电压。 还描述了相关方法。

    Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure
    3.
    发明授权
    Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure 有权
    闪存器件和操作方法，用于在擦除期间同时向虚拟存储器单元和常规存储器单元施加不同的偏置电压

    公开(公告)号：US08699274B2

    公开(公告)日：2014-04-15

    申请号：US13680812

    申请日：2012-11-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byeong-In Choe

    IPC: G11C16/28

    CPC classification number: G11C16/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30

    Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

    Abstract translation: 诸如NAND闪存器件的集成电路闪存器件包括常规闪存单元阵列，虚拟闪存单元阵列和擦除控制器。 擦除控制器被配置为在集成电路快闪存储器件的擦除操作期间同时向虚拟闪存单元施加不同于常规闪存单元的预定偏置电压。 还描述了相关方法。

    Nonvolatile memory device and an erasing method thereof
    4.
    发明授权
    Nonvolatile memory device and an erasing method thereof 有权
    非易失性存储器件及其擦除方法

    公开(公告)号：US09558834B2

    公开(公告)日：2017-01-31

    申请号：US14887454

    申请日：2015-10-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byeong-In Choe ,  Mincheol Park ,  Dongseog Eun ,  Eunsuk Cho

    IPC: G11C16/04 ,  G11C16/14 ,  G11C7/04 ,  G11C16/32

    CPC classification number: G11C16/14 ,  G11C7/04 ,  G11C16/32

    Abstract: An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.

    Abstract translation: 非易失性存储器件的擦除方法包括向衬底施加擦除电压; 感测存储单元阵列的温度; 基于所述存储单元阵列的温度来设置延迟时间，其中所述延迟时间响应于所述擦除电压被施加到所述衬底而开始; 在延迟时间内将接地电压施加到接地选择晶体管的接地选择线; 并在延迟时间后增加接地选择线的电压。

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