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    Methods of fabricating three dimensional semiconductor memory devices
    5.
    发明授权
    Methods of fabricating three dimensional semiconductor memory devices 有权
    制造三维半导体存储器件的方法

    公开(公告)号：US09048138B2

    公开(公告)日：2015-06-02

    申请号：US14281482

    申请日：2014-05-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hui-Chang Moon ,  Sung-Min Hwang ,  Woonkyung Lee

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L27/115 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

    Abstract: A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

    Abstract translation: 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells
    6.
    发明授权
    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells 有权
    包括接地选择晶体管和第一和第二虚拟存储器单元的非易失性存储器件的操作方法

    公开(公告)号：US09548123B2

    公开(公告)日：2017-01-17

    申请号：US14820703

    申请日：2015-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byeong-In Choe ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim ,  Woonkyung Lee

    IPC: G11C16/00 ,  G11C7/00 ,  H01L29/00 ,  H01L27/11 ,  G11C16/14 ,  G11C7/14 ,  G11C16/04 ,  G11C16/30 ,  H01L29/792 ,  H01L27/115 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/14 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    Abstract: A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

    Abstract translation: 非易失性存储器件包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。 所述方法可以包括将字线擦除电压施加到连接到所述单元串的存储单元的字线; 连接到单元串的地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

    Three-dimensional semiconductor device
    10.
    发明授权
    Three-dimensional semiconductor device 有权
    三维半导体器件

    公开(公告)号：US09202570B2

    公开(公告)日：2015-12-01

    申请号：US14142158

    申请日：2013-12-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Wonseok Cho

    IPC: H01L29/40 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

    CPC classification number: G11C16/0483 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

    Abstract translation: 三维半导体器件包括在第一和第二接触区域之间具有单元阵列区域的衬底。 第一堆叠包括垂直设置在基板上的多个第一电极，第二堆叠包括垂直设置在第一堆叠上的多个第二电极。 第二堆叠被布置成暴露第一接触区域上的第一电极的端部并且在第二接触区域上重叠第一电极的端部。

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