公开(公告)号：US09343432B2

公开(公告)日：2016-05-17

申请号：US14094996

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chung-Sun Lee ,  Jung-Hwan Kim ,  Tae-Hong Kim ,  Hyun-Jung Song ,  Sun-Pil Youn

IPC: H01L23/48 ,  H01L21/82 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Abstract translation: 公开了一叠半导体芯片，半导体器件和制造方法。 堆叠的半导体芯片可以包括堆叠的第一芯片，第一芯片上的堆叠的第二芯片，导电凸块，均匀的整体底部填充材料和模制材料。 导电凸块可以在第一芯片的上表面和第二芯片的下表面之间延伸。 均匀整体的底部填充材料可以插入在第一芯片和第二芯片之间，封装导电凸块，并且沿着第二芯片的侧壁延伸。 均匀整体的底部填充材料可以具有在与第二芯片的上表面平行的方向上延伸并且位于第二芯片的上表面附近的上表面。 模制材料可以在第一芯片的上表面之上的均匀整体底部填充材料的外侧表面上，其中，从第一横截面轮廓的角度来看，模制材料通过均匀的积分与第二芯片的侧壁分离 底部填充材料，使得模制材料不接触第二芯片的侧壁。