公开(公告)号：US20130249045A1

公开(公告)日：2013-09-26

申请号：US13763309

申请日：2013-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sin-Woo Kang ,  Jang-Ho Kim ,  Woon-Seob Lee ,  Jong-Hoon Cho ,  Sung-Dong Cho ,  Yeong-Lyeol Park

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.

Abstract translation: 提供了一种在应力消除层中具有通孔结构的半导体器件。 半导体器件可以包括电路区域上的隔离层，通孔区域上的应力消除层以及应力消除层和衬底中的通孔结构。 应力消除层的厚度可以大于隔离层的厚度和阶梯形横截面。

公开(公告)号：US20160020145A1

公开(公告)日：2016-01-21

申请号：US14804831

申请日：2015-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Taek Lee ,  Eun-Ji Kim ,  Sin-Woo Kang ,  Yeong-Lyeol Park ,  Sung-Dong Cho

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/308 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/10126 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.

Abstract translation: 半导体器件包括衬底上的电路器件和衬底上的第一绝缘中间层并覆盖电路器件。 电极结构延伸穿过第一绝缘中间层并且至少部分地穿过衬底。 蚀刻停止层图案设置在与基板相对的第一绝缘层一侧的电极结构的侧壁上。 阻挡层图案设置在蚀刻停止层图案上。 该装置还包括互连结构，其包括穿过阻挡层图案的通孔部分，以与通孔电极结构接触，并且在通孔部分上具有与通孔部分不同的宽度的布线部分。 半导体器件还可以包括通过第一绝缘中间层电连接到电路器件的接触插塞。 接触插塞和通孔电极结构可以包括不同的金属。

公开(公告)号：US09559002B2

公开(公告)日：2017-01-31

申请号：US14804831

申请日：2015-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Taek Lee ,  Eun-Ji Kim ,  Sin-Woo Kang ,  Yeong-Lyeol Park ,  Sung-Dong Cho

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/762 ,  H01L23/48 ,  H01L25/065 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/10126 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.

Abstract translation: 半导体器件包括衬底上的电路器件和衬底上的第一绝缘中间层并覆盖电路器件。 电极结构延伸穿过第一绝缘中间层并且至少部分地穿过衬底。 蚀刻停止层图案设置在与基板相对的第一绝缘层一侧的电极结构的侧壁上。 阻挡层图案设置在蚀刻停止层图案上。 该装置还包括互连结构，其包括穿过阻挡层图案的通孔部分，以与通孔电极结构接触，并且在通孔部分上具有与通孔部分不同的宽度的布线部分。 半导体器件还可以包括通过第一绝缘中间层电连接到电路器件的接触插塞。 接触插塞和通孔电极结构可以包括不同的金属。

公开(公告)号：US08841754B2

公开(公告)日：2014-09-23

申请号：US13763309

申请日：2013-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sin-Woo Kang ,  Jang-Ho Kim ,  Woon-Seob Lee ,  Jong-Hoon Cho ,  Sung-Dong Cho ,  Yeong-Lyeol Park

IPC: H01L29/40 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.

Abstract translation: 提供了一种在应力消除层中具有通孔结构的半导体器件。 半导体器件可以包括电路区域上的隔离层，通孔区域上的应力消除层以及应力消除层和衬底中的通孔结构。 应力消除层的厚度可以大于隔离层的厚度和阶梯形横截面。

公开(公告)号：US08890282B2

公开(公告)日：2014-11-18

申请号：US14013086

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woon-Seob Lee ,  Sin-Woo Kang ,  Ki-Young Yun ,  Sung-Dong Cho ,  Eun-Ji Kim ,  Yeong-Lyeol Park

IPC: H01L21/70 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L23/585 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.

Abstract translation: 集成电路器件包括其上具有多个器件图案的衬底。 在衬底上设置器件隔离层，在器件隔离层和衬底上提供层间介质层，并且导电通孔延伸穿过层间介质层和器件隔离层并进入衬底。 导电通孔接触焊盘设置在与导电通孔电接触的层间电介质层上。 在平面图中，导电通孔接触焊盘被限制在层间介质层的区域和/或器件隔离层的使导电通孔接触焊盘与衬底电绝缘的区域中。 还讨论了相关的方法和设备。

公开(公告)号：US20140124951A1

公开(公告)日：2014-05-08

申请号：US14013086

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woon-Seob Lee ,  Sin-Woo Kang ,  Ki-Young Yun ,  Sung-Dong Cho ,  Eun-Ji Kim ,  Yeong-Lyeol Park

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/585 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit device includes a substrate having a plurality of device patterns thereon. A device isolation layer is provided on the substrate, an interlayer dielectric layer is provided on the device isolation layer and the substrate, and a conductive via extends through the interlayer dielectric layer and the device isolation layer and into the substrate. A conductive via contact pad is provided on the interlayer dielectric layer in electrical contact with the conductive via. In plan view, the conductive via contact pad is confined within an area of the interlayer dielectric layer and/or an area of the device isolation layer that electrically insulates the conductive via contact pad from the substrate. Related methods and devices are also discussed.

Abstract translation: 集成电路器件包括其上具有多个器件图案的衬底。 在衬底上设置器件隔离层，在器件隔离层和衬底上提供层间介质层，并且导电通孔延伸穿过层间介质层和器件隔离层并进入衬底。 导电通孔接触焊盘设置在与导电通孔电接触的层间电介质层上。 在平面图中，导电通孔接触焊盘被限制在层间介质层的区域和/或器件隔离层的使导电通孔接触焊盘与衬底电绝缘的区域中。 还讨论了相关的方法和设备。

公开(公告)号：US09418915B2

公开(公告)日：2016-08-16

申请号：US14526479

申请日：2014-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sin-Woo Kang ,  Sung-Dong Cho

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/06 ,  H01L21/74

CPC classification number: H01L23/481 ,  H01L21/74 ,  H01L21/76898 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a gate structure formed in the interlayer insulating layer, an isolation layer formed in the semiconductor substrate, a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer, and a first conduction type first impurity region coming in contact with the isolation layer and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括半导体衬底，形成在半导体衬底上的层间绝缘层，形成在层间绝缘层中的栅极结构，形成在半导体衬底中的隔离层，穿透半导体衬底的穿硅通孔， 层间绝缘层和隔离层以及与隔离层接触并形成为仅在半导体衬底中仅包围穿硅通孔的侧壁的一部分的第一导电型第一杂质区。

公开(公告)号：US09293415B2

公开(公告)日：2016-03-22

申请号：US14708800

申请日：2015-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Ji Kim ,  Sung-Dong Cho ,  Hyoung-Yol Mun ,  Yeong-Lyeol Park ,  Seung-Taek Lee

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/564 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV.

Abstract translation: 提供了包括用于减少电偶腐蚀的保护图案的半导体器件和形成半导体器件的方法。 半导体器件可以包括包括保留区（KOZ）和多个互连的衬底，其可以设置在衬底上的KOZ的外部。 半导体器件还可以包括KOZ中的硅通孔（TSV）。 TSV可以通过衬底。 半导体器件还可以包括可以与TSV电绝缘的保护图案，可以设置在KOZ中，并且可以包括与TSV不同的导电材料。 保护图案的下端可以设置在高于TSV的下端的水平。