公开(公告)号：US10937771B2

公开(公告)日：2021-03-02

申请号：US16430428

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichul Kim ,  Jae Choon Kim ,  Hansung Ryu ,  KyongSoon Cho ,  YoungSang Cho ,  Yeo-Hoon Yoon

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L29/06

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

公开(公告)号：US12272610B2

公开(公告)日：2025-04-08

申请号：US17160462

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung Ryu

IPC: H01L23/053 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

Abstract: A semiconductor package includes a substrate, a semiconductor stack mounted on the substrate, and a stiffener surrounding the semiconductor stack, the stiffener having an octagonal shape at an edge of an upper surface thereof. A minimum distance from one angular point of an upper surface of the substrate to the stiffener is determined based on the thickness of the substrate.

公开(公告)号：US10937667B2

公开(公告)日：2021-03-02

申请号：US15930935

申请日：2020-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US11574819B2

公开(公告)日：2023-02-07

申请号：US17188404

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US10347611B2

公开(公告)日：2019-07-09

申请号：US15406925

申请日：2017-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichul Kim ,  Jae Choon Kim ,  Hansung Ryu ,  KyongSoon Cho ,  YoungSang Cho ,  Yeo-Hoon Yoon

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L29/06

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

公开(公告)号：US10211070B2

公开(公告)日：2019-02-19

申请号：US15815032

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02

Abstract: A semiconductor device including a substrate, an insulating, layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US09978694B2

公开(公告)日：2018-05-22

申请号：US15495051

申请日：2017-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyongsoon Cho ,  Myoungkyun Kil ,  Hansung Ryu

IPC: H01L23/02 ,  H01L23/22 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first substrate, and a first semiconductor chip positioned above the first substrate. A second semiconductor chip is positioned above a top surface of the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the second semiconductor chip. A second substrate is disposed on the second semiconductor chip. The second substrate substantially covers a top surface of the second semiconductor chip. A mold layer is disposed between the first substrate and the second substrate.

公开(公告)号：US09324748B2

公开(公告)日：2016-04-26

申请号：US14152421

申请日：2014-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hansung Ryu ,  Seungkon Mok

IPC: H01L27/146 ,  H01L31/0203

CPC classification number: H01L27/14618 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, an image sensor chip mounted on the substrate, a holder disposed on the substrate and surrounding the image sensor chip, and the holder has an inner surface facing the image sensor chip and an outer surface opposite to the inner surface. The semiconductor package further includes a transparent cover combined with the holder, and the transparent cover is spaced apart from and faces the substrate. The holder includes: a hole penetrating the holder from the inner surface to the outer surface. In addition, the semiconductor package further includes a first stopper disposed in the hole and a second stopper disposed at a position corresponding to the hole on the outer surface of the holder.

Abstract translation: 半导体封装包括基板，安装在基板上的图像传感器芯片，设置在基板上并围绕图像传感器芯片的保持器，并且保持器具有面向图像传感器芯片的内表面和与内表面相对的外表面 。 半导体封装还包括与保持器组合的透明盖，并且透明盖与衬底间隔开并面对衬底。 保持器包括：从内表面到外表面穿过保持器的孔。 此外，半导体封装还包括设置在孔中的第一止动件和设置在与保持器的外表面上的孔对应的位置处的第二止动件。

公开(公告)号：US20250022812A1

公开(公告)日：2025-01-16

申请号：US18642633

申请日：2024-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hansung Ryu ,  Jongbeom Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip that includes a first semiconductor substrate that includes an active surface and an inactive surface opposite to each other and a plurality of first through silicon vias that penetrate through the first semiconductor substrate, and a plurality of second semiconductor chips that each include a second semiconductor substrate that includes an active surface and an inactive surface opposite to each other and a plurality of second through silicon vias that penetrates through the second semiconductor substrate. Each of the plurality of second semiconductor chips is stacked on the first semiconductor chip, such that the active surface of each second semiconductor substrate faces the inactive surface of the first semiconductor substrate, and the plurality of second semiconductor chips have the same vertical height.

公开(公告)号：US20240105657A1

公开(公告)日：2024-03-28

申请号：US18240273

申请日：2023-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung Ryu ,  Yongsung Park ,  Jongbeom Park ,  Junho Lee ,  Jihyun Lee

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13113 ,  H01L2224/13541 ,  H01L2224/13583 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/384

Abstract: A semiconductor package includes a first substrate, a first bonding pad on the first substrate, a solder ball on the first bonding pad, and a blocking layer on the solder ball, wherein a thickness of the blocking layer varies in a direction away from the first substrate.