公开(公告)号：US09651431B2

公开(公告)日：2017-05-16

申请号：US14136787

申请日：2013-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Choon Kim ,  Jichul Kim ,  Jin-Kwon Bae ,  Eunho Jung

IPC: G01K7/42 ,  G01K3/06

CPC classification number: G01K7/42 ,  G01K3/06 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip.

公开(公告)号：US09589842B2

公开(公告)日：2017-03-07

申请号：US14993054

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Choi ,  Donghan Kim ,  Jae Choon Kim ,  Jikho Song ,  Mitsuo Umemoto

IPC: H01L21/44 ,  H01L23/485 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection layer covering top surfaces of the semiconductor chips, forming a molding layer covering the support substrate and the protection layer, and etching the molding layer to expose the protection layer.

Abstract translation: 公开了制造半导体封装的方法。 该方法包括将半导体芯片布置在支撑基板上，形成覆盖半导体芯片顶表面的保护层，形成覆盖支撑基板和保护层的模制层，以及蚀刻模塑层以露出保护层。

公开(公告)号：US11502059B2

公开(公告)日：2022-11-15

申请号：US16724592

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung Hwang ,  Jae Choon Kim ,  Yun Seok Choi

IPC: H01L25/065 ,  H01L23/367

Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.

公开(公告)号：US09653373B2

公开(公告)日：2017-05-16

申请号：US14976218

申请日：2015-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Choon Kim ,  Heejung Hwang ,  Eon Soo Jang

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/367 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip on a package substrate, a heat spreader on the semiconductor chip, a molding layer, an adhesive film between the semiconductor chip and the heat spreader, and a through-hole passing through the heat spreader. The heat spreader includes a first surface and a second surface. The molding layer covers sidewalls of the semiconductor chip and the heat spreader and exposes the first surface of the heat spreader. The adhesive film is on the second surface of the heat spreader.

公开(公告)号：US10937771B2

公开(公告)日：2021-03-02

申请号：US16430428

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichul Kim ,  Jae Choon Kim ,  Hansung Ryu ,  KyongSoon Cho ,  YoungSang Cho ,  Yeo-Hoon Yoon

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L29/06

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

公开(公告)号：US10553513B2

公开(公告)日：2020-02-04

申请号：US15922478

申请日：2018-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Hyun Park ,  Jae Choon Kim

IPC: H01L27/146 ,  H01L23/34 ,  H01L23/31 ,  H04N5/225 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L25/065

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

公开(公告)号：US10510737B2

公开(公告)日：2019-12-17

申请号：US15786698

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US09679874B2

公开(公告)日：2017-06-13

申请号：US14938788

申请日：2015-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Kwon Bae ,  Jae Choon Kim ,  Jichul Kim ,  Kyol Park ,  Chajea Jo

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/00 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/3205 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first semiconductor package disposed on the substrate, and a second semiconductor package spaced apart from the first semiconductor package on the substrate. The second semiconductor package includes a semiconductor chip stacked on the substrate, an adhesion part covering the semiconductor chip, and a heat-blocking structure disposed between the substrate and the semiconductor chip. Heat generated from the first semiconductor package and transmitted to the second semiconductor package through the substrate is blocked by the heat-blocking structure.

公开(公告)号：US09671141B2

公开(公告)日：2017-06-06

申请号：US14961167

申请日：2015-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Choon Kim ,  Jichul Kim ,  Jin-Kwon Bae ,  Eunseok Cho

IPC: F25B21/00 ,  F25B21/02 ,  H01L35/32

CPC classification number: F25B21/02 ,  F25B2321/0212 ,  F25B2700/2107 ,  H01L35/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A device includes a first board having a first area and a second area not overlapping the first area; and a thermoelectric semiconductor disposed between the first board and the second board at the first area of the first board configured to supply a voltage to the thermoelectric semiconductor; a package disposed at the second area of the first board.

公开(公告)号：US20250015049A1

公开(公告)日：2025-01-09

申请号：US18412447

申请日：2024-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo Park ,  Sunggu Kang ,  Jae Choon Kim ,  Taehwan Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package includes a redistribution line structure that has a redistribution line layer. A first semiconductor chip is disposed above the redistribution line structure and includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness. A sub-semiconductor package includes a second semiconductor chip and is disposed above the second region of the first semiconductor chip. A silicon through via penetrates the second region of the first semiconductor chip and electrically connects the sub-semiconductor package with the redistribution line structure. A sealant seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package. The sub-semiconductor package is disposed within the second region of the first semiconductor chip.