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公开(公告)号：US10135605B2
公开(公告)日：2018-11-20
申请号：US15794573
申请日：2017-10-26
发明人： Byoung-Joo Yoo , Kyung-Seok Song , Ho-Bin Song
摘要： A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.
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公开(公告)号：US11522736B2
公开(公告)日：2022-12-06
申请号：US17461070
申请日：2021-08-30
发明人： Byeong Gyu Park , Jun Han Bae , Yun Geun Nam , Jae Hyun Park , Gyeong Seok Song , Ho-Bin Song
摘要： An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.
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公开(公告)号：US09071237B2
公开(公告)日：2015-06-30
申请号：US14207751
申请日：2014-03-13
发明人： Cheon-Oh Lee , Tae-Pyeong Kim , Jung-Myung Choi , Sung-Jun Kim , Ho-Bin Song , Han-Kyul Lim
CPC分类号： H03K5/1565
摘要： A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.
摘要翻译： 数字占空比校正电路包括占空比控制器和数字占空比控制代码发生器。 占空比控制器通过基于数字占空比控制代码补偿第一和第二输入时钟信号的占空比来产生第一和第二输出时钟信号。 数字占空比控制码发生器基于通过转换第一输出时钟信号和第二输出时钟信号的占空比信息而获得的频率值来生成数字占空比控制码。
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4.发明授权Semiconductor device compensating for internal skew and operating method thereof 有权补偿内部偏斜的半导体器件及其操作方法公开(公告)号：US08941425B2
公开(公告)日：2015-01-27
申请号：US14136582
申请日：2013-12-20
发明人： Ho-Bin Song , Tae-Pyeong Kim , Cheon-Oh Lee
CPC分类号： H03K5/153
摘要： Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.
摘要翻译： 提供了用于补偿内部偏斜而不用外部设备进行训练的半导体器件。 半导体器件包括：信号生成单元，被配置为产生并输出参考信号;第一接收单元，被配置为接收参考信号并输出第一输出信号;第二接收单元，被配置为接收参考信号并输出第二输出信号 延迟单元，被配置为将所述第一输出信号延迟一定时间并输出延迟信号，所述采样单元被配置为基于所述延迟信号对所述第二输出信号进行采样并输出采样数据;以及歪斜控制单元， 基于采样数据的延迟单元。
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公开(公告)号：US11901967B2
公开(公告)日：2024-02-13
申请号：US17380779
申请日：2021-07-20
发明人： Byeong Gyu Park , Jae Hyun Park , Jun Han Bae , Ho-Bin Song
IPC分类号： H04B3/14
CPC分类号： H04B3/14
摘要： Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.
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公开(公告)号：US11733727B2
公开(公告)日：2023-08-22
申请号：US17680386
申请日：2022-02-25
发明人： Junhan Bae , Gyeongseok Song , Kyeong-Joon Ko , Jaehyun Park , Hajung Park , Ho-Bin Song
CPC分类号： G05F3/205 , H03F3/16 , H03K17/223
摘要： Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.
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