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    Memory systems with ZQ global management and methods of operating same
    2.
    发明授权
    Memory systems with ZQ global management and methods of operating same 有权

    公开(公告)号：US10284198B2

    公开(公告)日：2019-05-07

    申请号：US15282291

    申请日：2016-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Yeol Lee ,  Seokil Kim ,  Hoiju Chung ,  Yongjae Shin ,  YouKeun Han

    IPC: H03K19/00 ,  G11C7/10

    Abstract: A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.

    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF ERROR CORRECTION OF THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF ERROR CORRECTION OF THE SAME 审中-公开
    半导体存储器件，包括其的存储器系统及其错误校正方法

    公开(公告)号：US20160350181A1

    公开(公告)日：2016-12-01

    申请号：US15156804

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguhn CHA ,  Hoiju Chung ,  Uksong Kang ,  Chulwoo Park

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  H03M13/1575

    Abstract: A semiconductor memory device capable of detecting a miscorrected bit generated in the semiconductor memory device outside the semiconductor memory device and a memory system including the semiconductor memory device are disclosed. The semiconductor memory device may generate first check bits based on first data received from the outside, divide an error correcting code (ECC) code word including the first data and the first check bits into a plurality of code word groups, and dispose a miscorrected bit, caused by error bits included in a first ECC code word group, in another ECC code word group rather than the first ECC code word group.

    Abstract translation: 公开了一种半导体存储器件，其能够检测在半导体存储器件外部的半导体存储器件中产生的错误校正位和包括该半导体存储器件的存储器系统。 半导体存储器件可以基于从外部接收的第一数据生成第一校验位，将包括第一数据和第一校验位的纠错码（ECC）码字分成多个码字组，并且配置未校正位 由包含在第一ECC码字组中的错误位引起的，在另一ECC码字组而不是第一ECC码字组中引起的。

    Semiconductor memory device, memory system including the same, and method of error correction of the same
    5.
    发明授权
    Semiconductor memory device, memory system including the same, and method of error correction of the same 有权

    公开(公告)号：US10140176B2

    公开(公告)日：2018-11-27

    申请号：US15156804

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguhn Cha ,  Hoiju Chung ,  Uksong Kang ,  Chulwoo Park

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  G11C29/02 ,  G11C29/42

    Abstract: An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively. For each parity generator matrix group of the first parity generator matrix, a result value of a bit-by-bit exclusive OR (XOR) operation performed on any two columns included in the parity generator matrix group is equal to a column number of a column that is not included in the parity generator matrix group. Thus, when a first ECC code word group, from among the plurality of ECC code word groups, includes error bits, a miscorrected bit that would be caused by the error bits as a result of performing an error correction operation on the first ECC code word group is located in an ECC code word group other than the first ECC code word group.

    Semiconductor memory device managing flexible refresh skip area
    6.
    发明授权
    Semiconductor memory device managing flexible refresh skip area 有权

    公开(公告)号：US11631449B2

    公开(公告)日：2023-04-18

    申请号：US16389905

    申请日：2019-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uksong Kang ,  Hoiju Chung

    IPC: G11C11/40 ,  G11C11/406 ,  G11C11/408

    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

    SEMICONDUCTOR MEMORY DEVICE MANAGING FLEXIBLE REFRESH SKIP AREA
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE MANAGING FLEXIBLE REFRESH SKIP AREA 审中-公开

    公开(公告)号：US20190244657A1

    公开(公告)日：2019-08-08

    申请号：US16389905

    申请日：2019-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uksong Kang ,  Hoiju Chung

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/4087

    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

    Semiconductor memory device managing flexible refresh skip area
    8.
    发明授权
    Semiconductor memory device managing flexible refresh skip area 有权

    公开(公告)号：US10311936B2

    公开(公告)日：2019-06-04

    申请号：US15233942

    申请日：2016-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uksong Kang ,  Hoiju Chung

    IPC: G11C11/406 ,  G11C11/408

    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

    MEMORY SYSTEMS WITH ZQ GLOBAL MANAGEMENT AND METHODS OF OPERATING SAME
    9.
    发明申请
    MEMORY SYSTEMS WITH ZQ GLOBAL MANAGEMENT AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20170099050A1

    公开(公告)日：2017-04-06

    申请号：US15282291

    申请日：2016-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Yeol Lee ,  Seokil Kim ,  Hoiju Chung ,  Yongjae Shin ,  YouKeun Han

    IPC: H03K19/00 ,  G11C7/10

    CPC classification number: H03K19/0005 ,  G11C7/1057 ,  G11C2207/2254

    Abstract: A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.

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