公开(公告)号：US10756059B2

公开(公告)日：2020-08-25

申请号：US16157642

申请日：2018-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Sanghoon Joo ,  Jong-Ryun Choi ,  Jin-Ho Choi

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/58 ,  H01L23/60 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.

公开(公告)号：US20180107387A1

公开(公告)日：2018-04-19

申请号：US15842295

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee NAM ,  Ji Hun OH ,  Shinyoung YI ,  Jong-Ryun CHOI

IPC: G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G06F13/40 ,  G06F13/16 ,  G06F12/02 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US09857973B1

公开(公告)日：2018-01-02

申请号：US15584356

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C8/12 ,  G06F13/40 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US10650871B2

公开(公告)日：2020-05-12

申请号：US16118863

申请日：2018-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Sanghune Park

IPC: G11C7/22 ,  G06F13/16 ,  H03K19/20 ,  H03K19/21

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

公开(公告)号：US10586575B2

公开(公告)日：2020-03-10

申请号：US16211777

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Hyungkweon Lee

IPC: G11C7/22 ,  G06F13/16 ,  H03K19/20

Abstract: An electronic circuit including: a first delay line circuit to generate a first data strobe by delaying a second data strobe, such that an edge of the first data strobe is aligned within a first time interval; and a sampling circuit to sample the first data signal at the edge of the first data strobe, wherein plural data signals include the first data signal and a second data signal, wherein timings of the plural data signals deviate from a reference timing of a reference data strobe by plural time lengths, wherein the first data signal deviates from the reference timing by a first time length of the plural time lengths, and wherein an edge of the second data strobe is aligned within a second time interval, wherein a timing of the second data signal deviates from the reference timing by a shortest time length of the plural time lengths.

公开(公告)号：US10073619B2

公开(公告)日：2018-09-11

申请号：US15842295

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G06F13/40 ,  G11C5/04 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US11200928B2

公开(公告)日：2021-12-14

申请号：US16871096

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Sanghune Park

IPC: G11C7/22 ,  G06F13/16 ,  H03K19/20 ,  H03K19/21

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

公开(公告)号：US10115706B2

公开(公告)日：2018-10-30

申请号：US15277339

申请日：2016-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Sanghoon Joo ,  Jong-Ryun Choi ,  Jin-Ho Choi

IPC: H01L23/58 ,  H01L25/065 ,  H01L23/50 ,  H01L23/60 ,  H01L23/00

Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.

公开(公告)号：US20180018092A1

公开(公告)日：2018-01-18

申请号：US15584356

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.