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    Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device
    1.
    发明授权
    Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device 有权
    具有根据温度的放松定时参数的存储器件，其操作方法以及使用存储器件的存储器控​​制器和存储器系统

    公开(公告)号：US09465757B2

    公开(公告)日：2016-10-11

    申请号：US14290997

    申请日：2014-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Uk-song Kang ,  Chul-woo Park ,  Seong-young Seo

    IPC: G06F12/02 ,  G06F13/16 ,  G11C11/406

    CPC classification number: G06F13/1689 ,  G11C7/04 ,  G11C7/1045 ,  G11C11/40626 ,  G11C11/4076

    Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

    Abstract translation: 提供了一种根据温度的轻松的时序要求规范使用的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统。 存储装置在第一温度下具有第一定时特性，在第二温度下具有长于第一定时特性的第二定时特性。 如果存储器件的温度高于参考温度，则存储器控制器控制第一定时特性作为存储器件的定时要求指定。 如果存储器件的温度低于参考温度，则存储器控制器控制第二定时特性作为存储器件的定时要求规范。

    MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE 有权
    具有根据温度的放松时序参数的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统

    公开(公告)号：US20140359242A1

    公开(公告)日：2014-12-04

    申请号：US14290997

    申请日：2014-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Uk-song Kang ,  Chul-woo Park ,  Seong-young Seo

    IPC: G06F13/16

    CPC classification number: G06F13/1689 ,  G11C7/04 ,  G11C7/1045 ,  G11C11/40626 ,  G11C11/4076

    Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

    Abstract translation: 提供了一种根据温度的轻松的时序要求规范使用的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统。 存储装置在第一温度下具有第一定时特性，在第二温度下具有长于第一定时特性的第二定时特性。 如果存储器件的温度高于参考温度，则存储器控制器控制第一定时特性作为存储器件的定时要求指定。 如果存储器件的温度低于参考温度，则存储器控制器控制第二定时特性作为存储器件的定时要求规范。

    SEMICONDUCTOR MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME 有权
    具有可调整刷新周期的半导体存储器件，包含其的存储器系统及其操作方法

    公开(公告)号：US20140085999A1

    公开(公告)日：2014-03-27

    申请号：US14014490

    申请日：2013-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uk-song Kang

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C5/04 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  G11C2211/4065 ,  G11C2211/4068

    Abstract: A semiconductor memory device comprises a cell array comprising a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells.

    Abstract translation: 一种半导体存储器件，包括：包括多个单元区域的单元阵列;行解码器，被配置为基于计数地址来驱动对应于要执行刷新操作的单元区域的行;以及刷新地址生成器， 所述计数地址和修改的地址响应于控制信号，其中所述修改的地址是通过反转所述计数地址的至少一个位而产生的，并且其中所述半导体存储器件对对应于所述计数的第一单元区域执行并发刷新操作 地址和对应于第二小区区域被确定具有弱小区的修改地址的第二小区区域。

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