公开(公告)号：US10720447B2

公开(公告)日：2020-07-21

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L21/28 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US20190341400A1

公开(公告)日：2019-11-07

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/311 ,  H01L29/06 ,  H01L21/28 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/51 ,  H01L29/10

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US10411034B2

公开(公告)日：2019-09-10

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US10355099B2

公开(公告)日：2019-07-16

申请号：US15871055

申请日：2018-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Jun Kyu Yang ,  Young Jin Noh ,  Jae Young Ahn ,  Jae Hyun Yang ,  Dong Chul Yoo ,  Jae Ho Choi

IPC: H01L29/51 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

公开(公告)号：US20190157293A1

公开(公告)日：2019-05-23

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/0223 ,  H01L21/31111 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.