公开(公告)号：US20190341400A1

公开(公告)日：2019-11-07

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/311 ,  H01L29/06 ,  H01L21/28 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/51 ,  H01L29/10

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US20190157293A1

公开(公告)日：2019-05-23

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/0223 ,  H01L21/31111 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US10720447B2

公开(公告)日：2020-07-21

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L21/28 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US20210091782A1

公开(公告)日：2021-03-25

申请号：US15931729

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Jang ,  Yong Lim ,  Seung Hyun Oh ,  Jae Hoon Lee

IPC: H03M1/46 ,  H03K5/24

Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.

公开(公告)号：US10411034B2

公开(公告)日：2019-09-10

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US10359799B2

公开(公告)日：2019-07-23

申请号：US15914095

申请日：2018-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Jang ,  Seung Hyun Oh ,  Jong Woo Lee

IPC: G05F3/16 ,  H03K17/567

Abstract: A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.

公开(公告)号：US11018685B2

公开(公告)日：2021-05-25

申请号：US15931729

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Jang ,  Yong Lim ,  Seung Hyun Oh ,  Jae Hoon Lee

IPC: H03M1/38 ,  H03M1/46 ,  H03K5/24 ,  H03M1/00 ,  H03M1/12 ,  H03M1/06 ,  H03M1/10

Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.