公开(公告)号：US11501953B2

公开(公告)日：2022-11-15

申请号：US16361341

申请日：2019-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Bo Shim ,  Doug Yong Sung ,  Young Jin Noh ,  Yong Woo Lee ,  Ji Soo Im ,  Hyeong Mo Kang ,  Peter Byung H Han ,  Cheon Kyu Lee ,  Masato Horiguchi

IPC: H01L21/00 ,  H01J37/32 ,  H01L21/683 ,  H03H7/38 ,  H03H7/01 ,  H01L21/67

Abstract: Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.

公开(公告)号：US10720447B2

公开(公告)日：2020-07-21

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L21/28 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US12125685B2

公开(公告)日：2024-10-22

申请号：US17975012

申请日：2022-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Soo Lee ,  Yoshihisa Hirano ,  Jae Hoon Kim ,  Young Jin Noh ,  Sung Moon Park ,  Seung Kyu Lim ,  Kyeong Seok Jeong ,  Hyung Kyu Choi

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32091

Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

公开(公告)号：US20220172926A1

公开(公告)日：2022-06-02

申请号：US17443535

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Wan Kim ,  Beom Rae Kim ,  Dong Hyeon Na ,  Young Jin Noh ,  Seung Bo Shim ,  Sang-Ho Lee ,  Yong Woo Lee ,  Jun Ho Lee ,  Dong Hee Han

IPC: H01J37/32

Abstract: A method for fabricating a semiconductor device includes providing a wafer on a lower electrode inside a plasma processing apparatus. A first power having a first and second frequency is provided to the lower electrode. A second power is provided to an RF induction electrode through the lower electrode. A third power having the second frequency is released outside of a chamber. A plasma process is performed on the wafer while the third power is released. The RF induction electrode is disposed inside an insulating plate surrounding a sidewall of the lower electrode. The RF induction electrode is spaced apart front the lower electrode. The RF induction electrode has an annular shape surrounding the sidewall of the lower electrode. The first power is controlled by a first controller, and the third power is controlled by a second controller different from the first controller.

公开(公告)号：US20190341400A1

公开(公告)日：2019-11-07

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/311 ,  H01L29/06 ,  H01L21/28 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/51 ,  H01L29/10

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US10411034B2

公开(公告)日：2019-09-10

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US10355099B2

公开(公告)日：2019-07-16

申请号：US15871055

申请日：2018-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Jun Kyu Yang ,  Young Jin Noh ,  Jae Young Ahn ,  Jae Hyun Yang ,  Dong Chul Yoo ,  Jae Ho Choi

IPC: H01L29/51 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

公开(公告)号：US20230047219A1

公开(公告)日：2023-02-16

申请号：US17975012

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Soo Lee ,  Yoshihisa Hirano ,  Jae Hoon KIm ,  Young Jin Noh ,  Sung Moon Park ,  Seung Kyu Lim ,  Kyeong Seok Jeong ,  Hyung Kyu Choi

IPC: H01L21/3065 ,  H01J37/32

Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

公开(公告)号：US20200258753A1

公开(公告)日：2020-08-13

申请号：US16596945

申请日：2019-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Soo LEE ,  Yoshihisa Hirano ,  Jae Hoon Kim ,  Young Jin Noh ,  Sung Moon Park ,  Seung Kyu Lim ,  Kyeong Seok Jeong ,  Hyung Kyu Choi

IPC: H01L21/3065 ,  H01J37/32

Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

公开(公告)号：US20190157293A1

公开(公告)日：2019-05-23

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/0223 ,  H01L21/31111 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.