公开(公告)号：US20230123891A1

公开(公告)日：2023-04-20

申请号：US18085949

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjo KIM ,  Sangki NAM ,  Jungmin KO ,  Kwonsang SEO ,  Seungbo SHIM ,  Younghyun JO

IPC: H01J37/32

Abstract: An upper electrode used for a substrate processing apparatus using plasma is provided. The upper electrode includes a bottom surface including a center region and an edge region having a ring shape and surrounding the center region, a first protrusion portion protruding toward plasma from the edge region and having a ring shape, wherein the first protrusion portion includes a first apex corresponding to a radial local maximum point toward the plasma, and a first distance, which is a radial-direction distance between the first apex and a center axis of the upper electrode, is greater than a radius of a substrate.

公开(公告)号：US20220139881A1

公开(公告)日：2022-05-05

申请号：US17574953

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun SONG ,  Eunkyul OH ,  Hyeongmun KANG ,  Jungmin KO

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

公开(公告)号：US20210398947A1

公开(公告)日：2021-12-23

申请号：US17352757

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insup SHIN ,  Hyeongmun KANG ,  Jungmin KO ,  Hwanyoung CHOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

公开(公告)号：US20230317418A1

公开(公告)日：2023-10-05

申请号：US18068778

申请日：2022-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin KO ,  Sangki NAM ,  Dougyong SUNG ,  Byeongsang KIM ,  Yunhwan KIM ,  Suyoung YOO ,  Namkyun KIM ,  Kuihyun YOON

IPC: H01J37/32

CPC classification number: H01J37/3244 ,  H01J37/32568 ,  H01J2237/3343 ,  H01J2237/2001

Abstract: A substrate processing apparatus includes a process chamber having an internal space; upper and lower electrode portions facing each other in the internal space; and a gas supply unit configured to supply cooling gas to a bottom surface of a substrate seated on the lower electrode portion. The gas supply unit may include a gas supply source outside the process chamber and configured to provide a cooling gas, and a gas filter connected to the gas supply source and including one or more wall surfaces at least partially defining a gas flow path for the cooling gas. The gas filter may include a first and second regions formed of respective materials having different dielectric constants. The first and second regions may be configured so that the cooling gas flowing along the gas flow path flows upwardly concurrently with colliding with a wall surface of the gas flow path.

公开(公告)号：US20220351947A1

公开(公告)日：2022-11-03

申请号：US17548775

申请日：2021-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuihyun YOON ,  Sang Ki NAM ,  Kwonsang SEO ,  Sungho JANG ,  Jungmin KO ,  Nam Kyun KIM ,  Tae-Hyun KIM ,  Seunghan BAEK ,  Seungbin AHN ,  Jungmo YANG ,  Changheon LEE ,  Kangmin JEON

IPC: H01J37/32

Abstract: A plasma confinement ring includes a lower ring, an upper ring on the lower ring, and a connection ring extended to connect the lower ring to the upper ring. The lower ring includes a lower center hole vertically penetrating the lower ring at a center of the lower ring and at least one slit penetrating the lower ring in a region outside the lower center hole. The slit is structured to pass a more amount of air or gas at a first portion closer to the center of the lower ring than at a second portion farther from the center of the lower ring.

公开(公告)号：US20210265315A1

公开(公告)日：2021-08-26

申请号：US17030588

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun SONG ,  Eunkyul OH ,  Hyeongmun KANG ,  Jungmin KO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

公开(公告)号：US20210066231A1

公开(公告)日：2021-03-04

申请号：US16846616

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae CHO ,  Jinyeol YANG ,  Jungmin KO ,  Seungduk BAEK

IPC: H01L23/00

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.