公开(公告)号：US09865552B2

公开(公告)日：2018-01-09

申请号：US15002749

申请日：2016-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Sung Ryu ,  Kyong-soon Cho

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114

Abstract: A water level package includes a substrate, a plurality of semiconductor chips mounted on the substrate, and molding members that contact the substrate and the plurality of semiconductor chips and are formed on the substrate. The molding members include two or more molding members that have coefficients of thermal expansion (CTEs) different from each other.

公开(公告)号：US10672694B2

公开(公告)日：2020-06-02

申请号：US15397970

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-suk Kim ,  Kyong-soon Cho ,  Shle-ge Lee ,  Yu-duk Kim

IPC: H01L23/498 ,  H05K3/46 ,  H01L21/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A printed circuit board (PCB) reducing a thickness of a semiconductor package and improving reliability of the semiconductor package, a semiconductor package including the PCB, and a method of manufacturing the PCB may be provided. The PCB may include a substrate base having at least one base layer, and a plurality of wiring layers disposed on a top surface and a bottom surface of the at least one base layer, the plurality of wiring layers defining a plurality of wiring patterns, respectively may be provided. An elastic modulus of a conductive material of one wiring pattern of at least one wiring layer from among the plurality of wiring layers may be less than a conductive material of another wiring pattern.

公开(公告)号：US09728497B2

公开(公告)日：2017-08-08

申请号：US15180070

申请日：2016-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yu-duk Kim ,  Kyong-soon Cho ,  Shle-ge Lee ,  Da-hee Park

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A substrate structure may include a base substrate, a plurality of unit substrate regions arranged on the base substrate in one or more rows and one or more columns and spaced apart from one another, and dummy substrate regions between the unit substrate regions. In a row direction or a column direction, a first pitch between central points of two adjacent unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other.