公开(公告)号：US10347527B2

公开(公告)日：2019-07-09

申请号：US15975003

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Rha ,  Kyoung Hee Nam ,  Jeonggil Lee ,  Hyunseok Lim ,  Seungjong Park ,  Seulgi Bae ,  Jaejin Lee ,  Kwangtae Hwang

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

公开(公告)号：US09997400B2

公开(公告)日：2018-06-12

申请号：US15332297

申请日：2016-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Rha ,  Kyoung Hee Nam ,  Jeonggil Lee ,  Hyunseok Lim ,  Seungjong Park ,  Seulgi Bae ,  Jaejin Lee ,  Kwangtae Hwang

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

公开(公告)号：US09142489B2

公开(公告)日：2015-09-22

申请号：US13962341

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Hei Seung Kim ,  Kyoung Hee Nam ,  Jongmyeong Lee ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05093 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48453 ,  H01L2224/48464 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48465 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件可以包括非平面导电图案。 非平面导电图案可以在绝缘层上并且可以在多个不同高度处接触连接端子。 还提供了形成半导体器件的相关方法。

公开(公告)号：US20140042633A1

公开(公告)日：2014-02-13

申请号：US13962341

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Hong ,  Hei Seung Kim ,  Kyoung Hee Nam ,  Jongmyeong Lee ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05093 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48453 ,  H01L2224/48464 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48465 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件可以包括非平面导电图案。 非平面导电图案可以在绝缘层上并且可以在多个不同高度处接触连接端子。 还提供了形成半导体器件的相关方法。