公开(公告)号：US11462528B2

公开(公告)日：2022-10-04

申请号：US16459725

申请日：2019-07-02

申请人： Samsung Electronics Co., Ltd.

发明人： Hyunmog Park ,  Daehyun Kim ,  Jinmin Kim ,  Hei Seung Kim ,  Hyunsik Park ,  Sangkil Lee

IPC分类号： H01L27/115 ,  H01L25/18 ,  G11C14/00 ,  G11C16/04 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/48 ,  G11C13/00 ,  H01L27/11529

摘要： Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

公开(公告)号：US20140287578A1

公开(公告)日：2014-09-25

申请号：US14297302

申请日：2014-06-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

摘要翻译： 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。

公开(公告)号：US12119336B2

公开(公告)日：2024-10-15

申请号：US17883682

申请日：2022-08-09

申请人： Samsung Electronics Co., Ltd.

发明人： Hyunmog Park ,  Daehyun Kim ,  Jinmin Kim ,  Hei Seung Kim ,  Hyunsik Park ,  Sangkil Lee

IPC分类号： H01L25/18 ,  G11C14/00 ,  G11C16/04 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00 ,  H10B41/00 ,  H10B41/27 ,  H10B43/27 ,  G11C13/00 ,  H10B41/41

CPC分类号： H01L25/18 ,  G11C14/0018 ,  G11C16/04 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  G11C13/0004 ,  H10B41/41

摘要： Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

公开(公告)号：US11018137B2

公开(公告)日：2021-05-25

申请号：US16442769

申请日：2019-06-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC分类号： H01L27/10 ,  G11C11/40 ,  H01L27/108 ,  G11C11/402

摘要： A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.

公开(公告)号：US20130147005A1

公开(公告)日：2013-06-13

申请号：US13707425

申请日：2012-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC分类号： H01L27/04

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

摘要翻译： 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。

公开(公告)号：US11862476B2

公开(公告)日：2024-01-02

申请号：US17076025

申请日：2020-10-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC分类号： H01L21/34 ,  H10B12/00 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L21/34 ,  H01L21/02 ,  H01L21/28 ,  H10B12/053 ,  H10B12/31 ,  H10B12/482

摘要： A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US20190296018A1

公开(公告)日：2019-09-26

申请号：US16185892

申请日：2018-11-09

申请人： Samsung Electronics Co., Ltd.

发明人： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC分类号： H01L27/108

摘要： A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US09070752B2

公开(公告)日：2015-06-30

申请号：US14297302

申请日：2014-06-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L27/04 ,  H01L21/288 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L23/522 ,  C25D7/12 ,  C25D5/08 ,  C25D17/00 ,  C25D3/38

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

摘要翻译： 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。

公开(公告)号：US11488956B2

公开(公告)日：2022-11-01

申请号：US17313570

申请日：2021-05-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC分类号： H01L27/10 ,  H01L27/108 ,  G11C11/402

摘要： A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

公开(公告)号：US20210057417A1

公开(公告)日：2021-02-25

申请号：US17076025

申请日：2020-10-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC分类号： H01L27/108

摘要： A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.