公开(公告)号：US20140273382A1

公开(公告)日：2014-09-18

申请号：US14289076

申请日：2014-05-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jinho DO ,  Hajin LIM ,  WeonHong KIM ,  Kyungil HONG ,  Moonkyun SONG

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

摘要翻译： 准备包括NMOS晶体管区域和PMOS晶体管区域的衬底。 在PMOS晶体管区域上形成硅 - 锗层。 氮原子注入硅 - 锗层的上部。 在NMOS晶体管区域和PMOS晶体管区域上形成第一栅极电介质层。 在形成第一栅极介电层之前，将氮原子注入硅 - 锗层的上部。

公开(公告)号：US20210040616A1

公开(公告)日：2021-02-11

申请号：US16891177

申请日：2020-06-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Junghwan PARK ,  Younghyun KIM ,  Sechung OH ,  Jungmin LEE ,  Kyungil HONG

IPC分类号： C23C16/455 ,  B05B1/18 ,  C23C16/458 ,  C23C16/06 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

摘要： A shower head for a substrate treating apparatus and a substrate treating apparatus including the shower head, the shower head including a central head at a central portion of the shower head, the central head having a plurality of central holes through which a first injection gas is injectable; and a peripheral head at a peripheral portion of the shower head to enclose the central head, the peripheral head having a plurality of peripheral holes through which a second injection gas is injectable, wherein a total hole area of the peripheral holes is smaller than a total hole area of the central holes.

公开(公告)号：US20220254994A1

公开(公告)日：2022-08-11

申请号：US17466246

申请日：2021-09-03

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungil HONG ,  Jungmin LEE ,  Younghyun KIM ,  Junghwan PARK ,  Heeju SHIN ,  Se Chung OH

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

摘要： A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.

公开(公告)号：US20140175569A1

公开(公告)日：2014-06-26

申请号：US14190346

申请日：2014-02-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： WeonHong KIM ,  Dae-Kwon JOO ,  Hajin LIM ,  Jinho DO ,  Kyungil HONG ,  Moonkyun SONG

IPC分类号： H01L29/51

CPC分类号： H01L29/512 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

摘要翻译： 制造半导体器件的方法包括在半导体层上形成下界面层，下界面层为氮化物层，在下界面层上形成中间界面层，中间界面层为氧化物层，形成 中间界面层上的高k电介质层。 高k电介质层的介电常数高于下界面层和中间界面层的介电常数。

公开(公告)号：US20240090338A1

公开(公告)日：2024-03-14

申请号：US18308401

申请日：2023-04-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyungil HONG ,  Junghwan PARK ,  Gyuwon KIM ,  Yeonho CHOI

IPC分类号： H10N50/10 ,  G11C5/08 ,  H10B61/00

CPC分类号： H10N50/10 ,  G11C5/08 ,  H10B61/22

摘要： A magnetic memory device may include a substrate, an data storage pattern disposed on the substrate, and a lower contact plug between the substrate and the data storage pattern, the lower contact plug may include a lower insulating pattern, a lower contact pattern on the lower insulating pattern, and a lower barrier pattern extending along a lower surface and a side surface of the lower insulating pattern and a side surface of the lower contact pattern.

公开(公告)号：US20210043828A1

公开(公告)日：2021-02-11

申请号：US16793336

申请日：2020-02-18

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungil HONG ,  Younghyun KIM ,  Junghwan PARK ,  Sechung OH ,  Jungmin LEE

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L27/24 ,  H01L27/1159 ,  H01L43/08 ,  H01L43/12

摘要： A semiconductor device includes a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A blocking layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the blocking layer. An upper interconnection is on the upper insulating layer. An upper plug is connected to the upper interconnection and a corresponding one of the plurality of MTJ structures and extends into the upper insulating layer and the blocking layer. The blocking layer includes a material having a higher absorbance constant than the upper insulating layer.

公开(公告)号：US20190165261A1

公开(公告)日：2019-05-30

申请号：US16009556

申请日：2018-06-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sang-Kuk KIM ,  Oik KWON ,  Dongkyu LEE ,  Kyungil HONG

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02

摘要： A method of fabricating a magnetic memory device may include forming a magnetic tunnel junction layer on a substrate, sequentially forming a top electrode pattern and a mask pattern on the magnetic tunnel junction layer, patterning the magnetic tunnel junction layer using the mask pattern and the top electrode pattern as a first etch mask to form a magnetic tunnel junction pattern, forming a protection layer on side surfaces of the mask pattern, the top electrode pattern, and the magnetic tunnel junction pattern, the protection layer being extended to cover a first top surface of the mask pattern, removing a portion of the protection layer on the first top surface of the mask pattern to expose the first top surface of the mask pattern, and removing the mask pattern to expose a second top surface of the top electrode pattern.