公开(公告)号：US10076801B2

公开(公告)日：2018-09-18

申请号：US15443347

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-woo Song ,  Sung-il Cho ,  Se-gi Byun ,  Jin Yu

IPC: B23K1/20 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  C01B31/02 ,  B23K1/19 ,  B82Y40/00 ,  B82Y30/00

CPC classification number: B23K1/203 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K2101/42 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/158 ,  H01L21/4853 ,  H01L21/4864 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/15311 ,  Y10S977/742 ,  Y10S977/745 ,  Y10S977/75 ,  Y10S977/752 ,  Y10S977/842 ,  Y10S977/89 ,  Y10S977/932

Abstract: A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

公开(公告)号：US10529816B2

公开(公告)日：2020-01-07

申请号：US15915508

申请日：2018-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong Lee ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/772 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US11588039B2

公开(公告)日：2023-02-21

申请号：US16694242

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong Lee ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/822 ,  H01L21/84

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US20200098882A1

公开(公告)日：2020-03-26

申请号：US16694242

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong LEE ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L21/822 ,  H01L29/06 ,  H01L29/786 ,  H01L21/28

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.