公开(公告)号：US10002822B2

公开(公告)日：2018-06-19

申请号：US15089604

申请日：2016-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： MuSeob Shin ,  Won-young Kim ,  Sanghyun Park ,  Jinchan Ahn

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

公开(公告)号：US09455244B2

公开(公告)日：2016-09-27

申请号：US14104459

申请日：2013-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MuSeob Shin

IPC: H01L21/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06145 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type.

Abstract translation: 半导体封装包括封装衬底。 第一半导体芯片安装在封装基板上。 第一半导体芯片包括形成在第一芯片区域的顶表面上的第一芯片区域和第一芯片焊盘。 第二半导体芯片安装在封装基板上。 第二半导体芯片包括形成在第二芯片区域的顶表面上的第二芯片区域和第二芯片焊盘。 具有沟槽的边界区域划分第一芯片区域和第二芯片区域。 第一芯片区域，第二芯片区域和边界区域共享一体式半导体衬底。

公开(公告)号：US10141255B2

公开(公告)日：2018-11-27

申请号：US15994004

申请日：2018-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： MuSeob Shin ,  Won-young Kim ,  Sanghyun Park ,  Jinchan Ahn

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.