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    NONVOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF 审中-公开

    公开(公告)号：US20200303011A1

    公开(公告)日：2020-09-24

    申请号：US16693925

    申请日：2019-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won PARK ,  Won Bo SHIM ,  Bong Soon LIM

    IPC: G11C16/16 ,  G11C16/12 ,  G11C16/34 ,  G11C16/24

    Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

    MEMORY DEVICE REDUCING I/O SIGNAL LINES THROUGH I/O MAPPING CONNECTION AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明公开
    MEMORY DEVICE REDUCING I/O SIGNAL LINES THROUGH I/O MAPPING CONNECTION AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240232066A1

    公开(公告)日：2024-07-11

    申请号：US18454293

    申请日：2023-08-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Won PARK ,  Jooyong PARK ,  Seokmin YOON ,  Bongsoon LIM

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/023 ,  G06F13/1668

    Abstract: Disclosed is a memory system including a memory device and a memory controller. The memory device includes a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads by a mapping connection. The memory controller configured to provide the input/output signals to the memory device. The second memory chip is configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip due to the mapping connection. The first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on the mapping connection.

    NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210027841A1

    公开(公告)日：2021-01-28

    申请号：US16991821

    申请日：2020-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Won PARK ,  Sang-Wan NAM ,  Ji Yeon SHIN ,  Won Bo SHIM ,  Jung-Yun YUN ,  Ji Ho CHO ,  Sang Gi HONG

    IPC: G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

    Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.

    ERASE METHOD OF NON-VOLATILE MEMORY DEVICE
    4.
    发明申请
    ERASE METHOD OF NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220310171A1

    公开(公告)日：2022-09-29

    申请号：US17840021

    申请日：2022-06-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won PARK ,  Won Bo SHIM ,  Bong Soon LIM

    IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34 ,  G11C16/12

    Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

    NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件，非易失性存储器件的编程方法和包括非易失性存储器件的存储器系统

    公开(公告)号：US20150043283A1

    公开(公告)日：2015-02-12

    申请号：US14523850

    申请日：2014-10-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DongHun KWAK ,  Sang-Won PARK ,  Won-Taeck JUNG

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of verification voltages having different levels according to a result of the state read operation. Also disclosed are methods using a plurality of verification voltages selected based on factors which may affect a threshold voltage shift or other characteristic representing the data of a memory cell after programming.

    Abstract translation: 公开了一种程序方法和非易失性存储装置。 该方法包括接收要在存储器单元中编程的程序数据; 读取存储单元以判断擦除状态和至少一个程序状态; 执行使用多个状态读取电压读取所述至少一个程序状态的状态读取操作; 以及根据状态读取操作的结果，使用具有不同电平的多个验证电压对存储器单元中的程序数据进行编程。 还公开了使用基于可能影响阈值电压偏移的因素而选择的多个验证电压的方法或者在编程之后表示存储器单元的数据的其他特性的方法。

    NONVOLATILE MEMORY DEVICE, VERTICAL NAND FLASH MEMORY DEVICE AND SSD DEVICE INCLUDING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE, VERTICAL NAND FLASH MEMORY DEVICE AND SSD DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200135758A1

    公开(公告)日：2020-04-30

    申请号：US16440299

    申请日：2019-06-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won PARK ,  Sang-Wan NAM ,  Bong-Soon LIM

    IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11573 ,  G06F3/06

    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

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