公开(公告)号：US20240387420A1

公开(公告)日：2024-11-21

申请号：US18438335

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon Kwon ,  Jihun Jung ,  Yeongkwon Ko

IPC: H01L23/00 ,  H01L25/065

Abstract: The present disclosure relates to a semiconductor package including: a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip; and at least one bump structure disposed between the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a first bump pad and a second bump pad with different planar areas.

公开(公告)号：US20240321667A1

公开(公告)日：2024-09-26

申请号：US18387682

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Shin ,  Soyeon Kwon ,  Unbyoung Kang ,  Yeongkwon Ko

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/3185 ,  H01L21/568 ,  H01L21/78 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/13014 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0665

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface opposite to the first surface, a second semiconductor chip stacked on the first surface of the first semiconductor chip, and a molding layer contacting the first surface of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer includes a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.

公开(公告)号：US20250079250A1

公开(公告)日：2025-03-06

申请号：US18810742

申请日：2024-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Kuyoung Kim

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a substrate structure, a plurality of semiconductor chips sequentially stacked on the substrate structure, a molding member on the substrate structure and surrounding side surfaces of the plurality of semiconductor chips, the molding member including a first material, and a first reforming portion in a side portion of the molding member, and extending horizontally in the side portion of the molding member to have a predetermined width from an outer side surface of the molding member. The first reforming portion may include a second material that is more brittle than the first material.

公开(公告)号：US12218096B2

公开(公告)日：2025-02-04

申请号：US17707007

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Yoonsung Kim ,  Teakhoon Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

公开(公告)号：US20240213109A1

公开(公告)日：2024-06-27

申请号：US18371714

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Chungsun Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L23/3178 ,  H01L23/291 ,  H01L24/08 ,  H01L24/16 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2924/1435 ,  H10B80/00

Abstract: Provided is a semiconductor package including a first semiconductor device including a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, and a trench extending into the first interconnect structure and a portion of the first semiconductor substrate, a second semiconductor device on the first semiconductor device, and a cover insulating layer on the first semiconductor device and a side surface of the second semiconductor device, the cover insulating layer including a first portion filling the trench included in the first semiconductor device and contacting the first semiconductor substrate.