-
1.发明授权公开(公告)号：US12189976B2
公开(公告)日：2025-01-07
申请号：US18506293
申请日：2023-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-Hoon Woo , Hak-Sun Kim , Kwang-Jin Lee , Su-Chang Jeon
Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.
-
公开(公告)号：US10593408B2
公开(公告)日：2020-03-17
申请号：US16191656
申请日：2018-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
-
公开(公告)号：US10102909B2
公开(公告)日：2018-10-16
申请号：US15484580
申请日：2017-04-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Su-Chang Jeon , Dong-Kyo Shim
Abstract: A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
-
Patent Agency Ranking
公开(公告)号：US11238942B2
公开(公告)日：2022-02-01
申请号：US17023556
申请日：2020-09-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , Il-Han Park , Ji-Young Lee , Su-Chang Jeon
Abstract: Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.
-
公开(公告)号：US10937508B2
公开(公告)日：2021-03-02
申请号：US16364588
申请日：2019-03-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , Il-Han Park , Ji-Young Lee , Su-Chang Jeon
IPC: G11C16/26 , G11C11/56 , G11C16/24 , G11C16/10 , G11C16/34 , G06F11/10 , G11C29/52 , G11C16/14 , G11C16/04
Abstract: Nonvolatile memory device includes a memory cell array including pages, each of the pages including memory cells storing data bits, each of the data bits being selectable by a different threshold voltage, a page buffer circuit coupled to the memory cell array through bit-lines, the page buffer circuit including page buffers to sense data from selected memory cells, and perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch configured to sequentially store results of the two sequential sensing operations, and a control circuit to control the page buffers to store a result of the first read operation, reset the latches after completion of the first read operation, and perform the second read operation based on a valley determined based on the result of the first read operation.
-
公开(公告)号：US20200098436A1
公开(公告)日：2020-03-26
申请号：US16364588
申请日：2019-03-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Bum Kim , II-Han Park , Ji-Young Lee , Su-Chang Jeon
Abstract: Nonvolatile memory device includes a memory cell array including pages, each of the pages including memory cells storing data bits, each of the data bits being selectable by a different threshold voltage, a page buffer circuit coupled to the memory cell array through bit-lines, the page buffer circuit including page buffers to sense data from selected memory cells, and perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch configured to sequentially store results of the two sequential sensing operations, and a control circuit to control the page buffers to store a result of the first read operation, reset the latches after completion of the first read operation, and perform the second read operation based on a valley determined based on the result of the first read operation.
-
公开(公告)号：US10395741B2
公开(公告)日：2019-08-27
申请号：US16139921
申请日：2018-09-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Su-Chang Jeon , Dong-Kyo Shim
Abstract: A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
-
公开(公告)号：US10170192B2
公开(公告)日：2019-01-01
申请号：US15717992
申请日：2017-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.012 seconds)
