公开(公告)号：US20230223353A1

公开(公告)日：2023-07-13

申请号：US17976775

申请日：2022-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Taesung Jeong ,  Doohwan Lee

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/5385 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/105 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.

公开(公告)号：US20250140755A1

公开(公告)日：2025-05-01

申请号：US19004937

申请日：2024-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo BYUN ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips.

公开(公告)号：US11784129B2

公开(公告)日：2023-10-10

申请号：US17183562

申请日：2021-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Taesung Jeong

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/20 ,  H01L2224/211 ,  H01L2224/214

Abstract: A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

公开(公告)号：US11676915B2

公开(公告)日：2023-06-13

申请号：US17241875

申请日：2021-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesung Jeong ,  Doohwan Lee ,  Hongwon Kim ,  Junggon Choi

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/6835 ,  H01L2224/16227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18161 ,  H01L2924/3512

Abstract: A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm3.

公开(公告)号：US12218099B2

公开(公告)日：2025-02-04

申请号：US17392511

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo Byun ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips.

公开(公告)号：US11088115B2

公开(公告)日：2021-08-10

申请号：US16685575

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo Byun ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.

公开(公告)号：US20240006342A1

公开(公告)日：2024-01-04

申请号：US18119327

申请日：2023-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Yieok Kwon ,  Sangkyu Lee ,  Taesung Jeong

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L23/295 ,  H01L24/16 ,  H01L2224/16227 ,  H10B80/00

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer; a semiconductor chip on a first surface of the first redistribution structure and including a connection pad electrically connected to the first redistribution layer; an encapsulant that surrounds at least a portion of the semiconductor chip; a second redistribution structure on the encapsulant and including a second redistribution layer; a through-via structure that extends through the encapsulant and electrically connects the first redistribution layer to the second redistribution layer; an organic material layer between the through-via structure and the encapsulant and having an elongation rate greater than an elongation rate of the encapsulant; and a bump structure on a second surface of the first redistribution structure.

公开(公告)号：US20220077078A1

公开(公告)日：2022-03-10

申请号：US17241875

申请日：2021-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesung Jeong ,  Doohwan Lee ,  Hongwon Kim ,  Junggon Choi

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm3.

公开(公告)号：US20200185357A1

公开(公告)日：2020-06-11

申请号：US16685575

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungsoo BYUN ,  Taesung Jeong ,  Younggwan Ko ,  Jaeean Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.