公开(公告)号：US09245827B2

公开(公告)日：2016-01-26

申请号：US14262693

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uk-song Kang ,  Dong-hyeon Jang ,  Seong-jin Jang ,  Hoon Lee ,  Jin-ho Kim ,  Nam-seog Kim ,  Byung-sik Moon ,  Woo-dong Lee

IPC: G11C5/06 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  G11C8/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/481 ,  G11C5/06 ,  G11C8/18 ,  H01L22/32 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract translation: 三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。 从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。 只有主芯片可以为通道提供负载。 可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。

公开(公告)号：US20140233292A1

公开(公告)日：2014-08-21

申请号：US14262693

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uk-song Kang ,  Dong-hyeon Jang ,  Seong-jin Jang ,  Hoon Lee ,  Jin-ho Kim ,  Nam-seog Kim ,  Byung-sik Moon ,  Woo-dong Lee

IPC: H01L23/48 ,  G11C8/18 ,  G11C5/06

CPC classification number: H01L23/481 ,  G11C5/06 ,  G11C8/18 ,  H01L22/32 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract translation: 三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。 从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。 只有主芯片可以为通道提供负载。 可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。