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    Integrated circuit with adaptability to a process-voltage-temperature (PVT) variation
    1.
    发明授权
    Integrated circuit with adaptability to a process-voltage-temperature (PVT) variation 有权

    公开(公告)号：US11086345B2

    公开(公告)日：2021-08-10

    申请号：US16935610

    申请日：2020-07-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok-won Lee ,  Nam-seog Kim

    IPC: G05F1/575

    Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

    Integrated circuit with adaptability to a process-voltage-temperature (PVT) variation
    5.
    发明授权
    Integrated circuit with adaptability to a process-voltage-temperature (PVT) variation 有权

    公开(公告)号：US10747250B2

    公开(公告)日：2020-08-18

    申请号：US16453149

    申请日：2019-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok-won Lee ,  Nam-seog Kim

    IPC: G05F1/575

    Abstract: An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

    Frequency divider and a transceiver including the same
    6.
    发明授权
    Frequency divider and a transceiver including the same 有权

    公开(公告)号：US10547315B2

    公开(公告)日：2020-01-28

    申请号：US16202172

    申请日：2018-11-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-won Choi ,  Nam-seog Kim

    IPC: H03K21/02 ,  H03K3/037 ,  H03K7/08 ,  H04B1/40

    Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature signal of the first output signal.

    FREQUENCY DIVIDER AND A TRANSCEIVER INCLUDING THE SAME
    9.
    发明申请
    FREQUENCY DIVIDER AND A TRANSCEIVER INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190165790A1

    公开(公告)日：2019-05-30

    申请号：US16202172

    申请日：2018-11-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-won Choi ,  Nam-seog Kim

    IPC: H03K21/02 ,  H03K3/037 ,  H03K7/08

    CPC classification number: H03K21/02 ,  H03K3/037 ,  H03K5/1565 ,  H03K7/08 ,  H03K21/40 ,  H04B1/40

    Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature signal of the first output signal.

    Digital-to-time converter and operating method thereof
    10.
    发明授权
    Digital-to-time converter and operating method thereof 有权

    公开(公告)号：US10122378B2

    公开(公告)日：2018-11-06

    申请号：US15869854

    申请日：2018-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Nam-seog Kim

    IPC: H03M1/82 ,  H03M1/78 ,  H03K5/135 ,  G04F10/00 ,  H03F3/217 ,  H03L7/097 ,  H03K5/131

    Abstract: A digital-to-time converter includes: a digital-to-analog converter configured to generate a precharge voltage corresponding to a value of a digital code; a ramp generator configured to precharge a capacitor connected to a first node based on the precharge voltage, and to charge or discharge the capacitor based on a reference current provided from a current source in response to a transition of an input clock signal to generate a ramp voltage in the first node; and a comparator configured to generate an output clock signal based on the ramp voltage, wherein the ramp generator includes: a first switching circuit configured to provide a first current path between a second node connected to the current source and the first node; and a second switching circuit configured to provide a second current path from a power supply voltage source to the second node.

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