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    Encoding and decoding of data using generalized LDPC codes
    1.
    发明授权
    Encoding and decoding of data using generalized LDPC codes 有权

    公开(公告)号：US12143123B2

    公开(公告)日：2024-11-12

    申请号：US18358660

    申请日：2023-07-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ariel Doubchak ,  Avner Dor ,  Yaron Shany ,  Tal Philosof ,  Yoav Shereshevski ,  Amit Berman

    IPC: H03M13/11 ,  H03M13/00

    Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

    Hardware architecture for local erasure correction in SSD/UFS via maximally recoverable codes
    4.
    发明授权
    Hardware architecture for local erasure correction in SSD/UFS via maximally recoverable codes 有权

    公开(公告)号：US11528037B1

    公开(公告)日：2022-12-13

    申请号：US17351107

    申请日：2021-06-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Amit Berman ,  Yaron Shany ,  Ariel Doubchak

    IPC: H03M13/15 ,  G06N3/04 ,  H03M13/00

    Abstract: A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix H1 of columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix H2 of columns of H located on non-erased coordinates of code C; a neural network that calculates matrix J1 that is an approximate inverse of matrix H1. The matrix J1 is used to determine new erasures in the parity matrix H and new erased coordinates. Matrices H1 and H2 are updated, and the updated H1 is provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J1, matrix H2, and a non-erased part of codeword C.

    Fast polynomial division by monomial for Reed-Solomon ELP maintenance
    5.
    发明授权
    Fast polynomial division by monomial for Reed-Solomon ELP maintenance 有权

    公开(公告)号：US12224769B2

    公开(公告)日：2025-02-11

    申请号：US18196581

    申请日：2023-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Amit Berman ,  Dikla Shapiro ,  Yaron Shany

    IPC: H03M13/15 ,  H03M13/00

    Abstract: Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a codeword from among a plurality of codewords stored in a storage device, wherein the codeword includes a plurality of frames; obtaining an initial error locator polynomial (ELP) corresponding to the codeword; decoding a frame of the plurality of frames; based on determining that the frame is successfully decoded, determine an updated ELP based on the initial ELP and information about the frame; and obtaining information bits corresponding to the codeword based on the updated ELP, wherein the updated ELP includes a plurality of updated coefficients, and wherein the updated ELP is determined by simultaneously calculating at least two updated coefficients from among the plurality of updated coefficients.

    Low-power error correction code computation in GF (2R)
    7.
    发明授权
    Low-power error correction code computation in GF (2R) 有权

    公开(公告)号：US11438013B2

    公开(公告)日：2022-09-06

    申请号：US16929983

    申请日：2020-07-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Avner Dor ,  Amit Berman ,  Ariel Doubchak ,  Elik Almog Sheffi ,  Yaron Shany

    IPC: H03M13/00 ,  H03M13/15

    Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ω=Σ0≤i≤r−1βi×αi wherein α is a fixed primitive element of F, and βi∈GF(2), wherein K=GF(2s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω1+α×ω2, ω1=Σ0≤i≤s−1 γi×δi∈K, ω2=Σ0≤i≤s−1 γi+s×δi∈K, and γ=[γ0, . . . , γr−1]T∈GF(2)r; accessing a first table with ω1 to obtain ω3=ω1−1, computing ω2×ω3 in field K, accessing a second table with ω2=ω3 to obtain (1+α×ω2×ω3)−1=ω4+α×ω5, wherein ω−1=(ω1×(1+α×ω2×ω3))−1=ω3×(ω4+α×ω5)=ω3×ω4+α×ω3×ω5; and computing products ω3×ω4 and ω3×ω5 to obtain ω−1=Σ0≤i≤s−1θi×δi+α·Σi≤i≤s−1θi+s=δi where θi∈GF(2).

    Efficient generalized tensor product codes encoding schemes
    8.
    发明授权
    Efficient generalized tensor product codes encoding schemes 有权

    公开(公告)号：US10333554B2

    公开(公告)日：2019-06-25

    申请号：US15639475

    申请日：2017-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Moshe Ben Ari ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong ,  Yaron Shany

    IPC: H03M13/00 ,  H03M13/15 ,  H03M13/29

    Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.

    Low-power systematic ECC encoder with balancing bits
    10.
    发明授权
    Low-power systematic ECC encoder with balancing bits 有权

    公开(公告)号：US12289119B2

    公开(公告)日：2025-04-29

    申请号：US18142703

    申请日：2023-05-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Idan Dekel ,  Amit Berman ,  Ariel Doubchak ,  Yaron Shany

    IPC: H03M13/39 ,  H03M13/15 ,  H03M13/19

    Abstract: Systems, devices, and methods for encoding information bits for storage, including obtaining information bits and a target constraints vector, placing the information bits in an input vector, setting balance bits included in the input vector to zero, encoding the input vector using a systematic code to obtain a preliminary codeword, applying a constraints matrix to the preliminary codeword to obtain a preliminary constraints vector, applying a transition matrix to a sum of the preliminary constraints vector and the target constraints vector to determine updated balance bits, obtaining an output codeword based on the information bits and the updated balance bits, and storing the output codeword in the storage device.

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