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    EFFICIENT SURVIVOR MEMORY ARCHITECTURE FOR SUCCESSIVE CANCELLATION LIST DECODING OF CHANNEL POLARIZATION CODES
    1.
    发明申请
    EFFICIENT SURVIVOR MEMORY ARCHITECTURE FOR SUCCESSIVE CANCELLATION LIST DECODING OF CHANNEL POLARIZATION CODES 审中-公开

    公开(公告)号：US20190058547A1

    公开(公告)日：2019-02-21

    申请号：US15680661

    申请日：2017-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eran Hof ,  Moshe Twitto ,  Jun Jin Kong

    IPC: H04L1/00 ,  H03M13/37 ,  H03M13/45

    Abstract: A method of storing survivor data generated while decoding channel polarization codes in a memory module includes setting a list size that corresponds to a number of decoder units used to decode the channel polarization codes, inputting a stream of input bits to the decoder units, and sequentially decoding the input bits. Each input bit is decoded using all previous input bits decoded before the each input bit. The method further includes selecting a plurality of survivor bits from among the decoded input bits, and storing the selected survivor bits in the memory module in a binary tree configuration. The number of edges in each level of the binary tree configuration does not exceed the list size.

    Methods of driving a memory
    3.
    发明授权
    Methods of driving a memory 有权
    驾驶记忆的方法

    公开(公告)号：US09105339B2

    公开(公告)日：2015-08-11

    申请号：US13799554

    申请日：2013-03-13

    Applicant: Samsung Electronics, Co., Ltd.

    Inventor： Moshe Twitto ,  Jun-Jin Kong

    IPC: G11C16/16 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/16 ,  G11C16/10 ,  G11C16/3445

    Abstract: Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased.

    Abstract translation: 驱动存储器的方法包括擦除存储器件的多个存储器单元，测试存储器单元是否已被擦除，并且如果多于存储器单元的预定百分比，则不再擦除存储器单元而对存储器单元进行编程，而是更少 比所有的记忆单元都被成功擦除。

    Efficient generalized tensor product codes encoding schemes
    4.
    发明授权
    Efficient generalized tensor product codes encoding schemes 有权

    公开(公告)号：US10333554B2

    公开(公告)日：2019-06-25

    申请号：US15639475

    申请日：2017-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Moshe Ben Ari ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong ,  Yaron Shany

    IPC: H03M13/00 ,  H03M13/15 ,  H03M13/29

    Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.

    Method and apparatus for encoding and decoding data in memory system
    5.
    发明授权
    Method and apparatus for encoding and decoding data in memory system 有权
    用于在存储器系统中对数据进行编码和解码的方法和装置

    公开(公告)号：US09384087B2

    公开(公告)日：2016-07-05

    申请号：US14542828

    申请日：2014-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moshe Twitto ,  Avner Dor ,  Jun Jin Kong ,  Jung Soo Chung

    IPC: H03M13/03 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00

    CPC classification number: G06F11/1012 ,  G06F11/108 ,  G06F2211/109 ,  H03M13/036 ,  H03M13/1157 ,  H03M13/118 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/611

    Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

    Abstract translation: 示例性实施例公开了用于在存储器系统中对数据进行编码和解码的方法和装置。 在根据发明构思的示例性实施例的编码方法中，基于被存储的数据和辅助数据的组合，根据被卡住的小区和基于关于被卡住的小区的坐标的信息的编码矩阵和 卡住细胞。 生成的码字包括对应于与被卡住的小区的坐标对应的地址处的卡住的小区的值的数据。 在根据发明构思的示例性实施例的解码方法中，可以通过将用于编码的编码矩阵的逆矩阵乘以码字来生成数据。

    Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID)
    7.
    发明授权
    Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID) 有权

    公开(公告)号：US10387254B2

    公开(公告)日：2019-08-20

    申请号：US15730943

    申请日：2017-10-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Yaron Shany ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong

    IPC: G06F11/10 ,  G06F3/06 ,  H03M13/15 ,  H03M13/29

    Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n−{tilde over (k)}j, where the first n-kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n−{tilde over (k)}j)(n−{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n−kl columns Tj and has k1−{tilde over (k)}j columns; finding a vector c−(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n−{tilde over (k)}j; and solving ( A | I ) ⁢ ( a b ) = ( Q j | T j ) ⁢ s ~ = T j ⁢ s ⁢ ⁢ where ⁢ ⁢ a = 0 ⁢ ⁢ and ⁢ ⁢ b = T j ⁢ s , where a=0 and b=Tjs, and codeword c is nonzero only on the last n−{tilde over (k)}j=n−kj bits.

    Memory controller, method of operating the same, and system including the same
    9.
    发明授权
    Memory controller, method of operating the same, and system including the same 有权
    内存控制器，操作方法以及包含其的系统

    公开(公告)号：US09354969B2

    公开(公告)日：2016-05-31

    申请号：US14208340

    申请日：2014-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Avner Dor ,  Jun Jin Kong ,  Chang Kyu Seol ,  Hong Rak Son

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1072 ,  G06F11/108

    Abstract: A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.

    Abstract translation: 使用存储器控制器处理数据的方法包括基于每个多级单元的当前单元状态来确定可以改变多个多电平单元中的每一个的至少一个单元状态，其中每个多电平单元 包括多个数据页; 当数据页的值基于映射到所述至少一个单元状态的映射值具有单个映射值并且生成关于所述卡位的卡位位数据时，将所述数据页之一确定为具有卡住位; 以及基于所述卡住的位数据对要存储在所述多级单元中的写入数据进行编码。

    Nonvolatile memory devices and methods of controlling the same
    10.
    发明授权
    Nonvolatile memory devices and methods of controlling the same 有权

    公开(公告)号：US10606760B2

    公开(公告)日：2020-03-31

    申请号：US15684252

    申请日：2017-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Elona Erez ,  Avner Dor ,  Moshe Twitto ,  Jun Jin Kong

    IPC: G06F12/1009 ,  G06F12/02

    Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

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