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    Semiconductor memory devices having enhanced refresh operations that inhibit row hammer hacking
    1.
    发明授权
    Semiconductor memory devices having enhanced refresh operations that inhibit row hammer hacking 有权

    公开(公告)号：US12236105B2

    公开(公告)日：2025-02-25

    申请号：US17934623

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Jin Cho ,  Jung Min You

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

    Semiconductor memory devices and methods of operating the same
    2.
    发明授权
    Semiconductor memory devices and methods of operating the same 有权

    公开(公告)号：US10156995B2

    公开(公告)日：2018-12-18

    申请号：US15398409

    申请日：2017-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Ye-Sin Ryu ,  Seong-Jin Cho

    IPC: G06F3/06 ,  H03M13/15 ,  G11C29/52 ,  G11C11/16 ,  G06F11/10 ,  H03M13/00 ,  G11C29/00 ,  G11C29/04

    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

    Memory device data loss prevention
    3.
    发明授权
    Memory device data loss prevention 有权

    公开(公告)号：US12183390B2

    公开(公告)日：2024-12-31

    申请号：US17953524

    申请日：2022-09-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hijung Kim ,  Jung Min You ,  Seong-Jin Cho

    IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4096 ,  G11C17/16

    Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.

    Memory device and memory system including the same
    4.
    发明授权
    Memory device and memory system including the same 有权

    公开(公告)号：US12182416B2

    公开(公告)日：2024-12-31

    申请号：US17885822

    申请日：2022-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Min You ,  Seong-Jin Cho

    IPC: G11C11/406 ,  G06F3/06 ,  G06F12/02 ,  G11C7/10

    Abstract: According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.

    SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED REFRESH OPERATIONS THAT INHIBIT ROW HAMMER HACKING
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES HAVING ENHANCED REFRESH OPERATIONS THAT INHIBIT ROW HAMMER HACKING 审中-公开

    公开(公告)号：US20230221869A1

    公开(公告)日：2023-07-13

    申请号：US17934623

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Jin Cho ,  Jung Min You

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0653

    Abstract: A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

    DEVICE AND METHOD FOR EVALUATING SYSTEM PERFORMANCE
    8.
    发明申请
    DEVICE AND METHOD FOR EVALUATING SYSTEM PERFORMANCE 审中-公开
    用于评估系统性能的装置和方法

    公开(公告)号：US20150269051A1

    公开(公告)日：2015-09-24

    申请号：US14418696

    申请日：2013-07-31

    Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

    Inventor： Ji-Hoon Park ,  Seung-Hyun Yoon ,  Seung-Wook Lee ,  Jae-Wook Jeon ,  Seong-Jin Cho

    IPC: G06F11/34 ,  G06Q10/06

    CPC classification number: G06F11/3409 ,  G06F11/3058 ,  G06F11/3414 ,  G06F11/3438 ,  G06Q10/0639

    Abstract: A device and a method for evaluating the performance of a system on the basis of a user experience are disclosed. To this end, experience information of a user according to the driving of an embedded system is collected on the basis of a predetermined or preset condition, and a scenario selection condition is set in order to select a scenario for evaluating the performance of the embedded system. An experience pattern of the user is analyzed by requisite experience information obtained from the collected experience information on the basis of the set scenario selection condition, and an optimal scenario for evaluating the performance of the embedded system is selected among a plurality of available scenarios on the basis of the results according to the analysis, thereby evaluating the performance of the embedded system using the selected scenario.

    Abstract translation: 公开了一种基于用户体验来评估系统的性能的装置和方法。 为此，基于预定或预设条件收集根据嵌入式系统的驱动的用户的体验信息，并且设置场景选择条件以便选择用于评估嵌入式系统的性能的场景 。 基于所设置的场景选择条件，从所收集的体验信息中获得的必要经验信息分析用户的体验模式，并且在多个可用场景中选择用于评估嵌入式系统的性能的最佳场景 根据分析结果的基础，从而使用所选场景评估嵌入式系统的性能。

    Memory device that stores number of activation times of word lines
    10.
    发明授权
    Memory device that stores number of activation times of word lines 有权

    公开(公告)号：US12040008B2

    公开(公告)日：2024-07-16

    申请号：US17953068

    申请日：2022-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seong-Jin Cho

    IPC: G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/4091 ,  H01L25/18

    CPC classification number: G11C11/4085 ,  G06F12/06 ,  G11C11/406 ,  G11C11/4091 ,  H01L25/18

    Abstract: A memory device including a memory bank array which includes a first edge memory block, a second edge memory block, and a plurality of memory blocks placed between the first edge memory block and the second edge memory block; a plurality of sense amplifiers between the plurality of memory blocks, and that connect a first bit line of a memory block on one side of each of the plurality of sense amplifiers and a first complementary bit line of a memory block on an other side of each of the plurality of sense amplifiers; a first edge sense amplifier connected to a second bit line and a second complementary bit line of the first edge memory block; and a second edge sense amplifier connected to a third bit line and a third complementary bit line of the second edge memory block.

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