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1.发明公开公开(公告)号：US20240282353A1
公开(公告)日：2024-08-22
申请号：US18654443
申请日：2024-05-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngcheon KWON , Jemin Ryu , Jaeyoun Youn , Haesuk Lee , Jihyun Choi
CPC classification number: G11C7/222 , G11C7/1048 , G11C7/1057 , G11C7/1084
Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
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公开(公告)号：US11636885B2
公开(公告)日：2023-04-25
申请号：US17574174
申请日：2022-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngcheon Kwon , Jemin Ryu , Jaeyoun Youn , Haesuk Lee , Jihyun Choi
Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
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公开(公告)号：US11232029B2
公开(公告)日：2022-01-25
申请号：US17003346
申请日：2020-08-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonsik Sohn , Hyunjoong Kim , Woongjae Song , Soowoong Ahn , Seunghyun Cho , Jihyun Choi
IPC: G11C8/00 , G06F12/06 , H01L23/48 , H01L25/065
Abstract: According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.
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公开(公告)号：US20220139433A1
公开(公告)日：2022-05-05
申请号：US17574174
申请日：2022-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngcheon Kwon , Jemin Ryu , Jaeyoun Youn , Haesuk Lee , Jihyun Choi
Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
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公开(公告)号：US10013341B2
公开(公告)日：2018-07-03
申请号：US15371825
申请日：2016-12-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Oh-Seong Kwon , Jinhyun Kim , Won-Hyung Song , Jihyun Choi
IPC: G06F12/00 , G06F12/02 , G06F3/06 , G11C8/18 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4076 , G11C11/408 , G11C11/4093
CPC classification number: G06F12/00 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F12/02 , G11C5/04 , G11C7/1042 , G11C7/1057 , G11C8/12 , G11C8/18 , G11C11/4076 , G11C11/408 , G11C11/4093 , G11C2207/2209
Abstract: A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The second memory area is accessed independently of the first memory area based on a usage selecting signal. The first and second memory areas share command and address lines, and perform a rank interleaving operation based on the usage selecting signal.
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Patent Agency Ranking
公开(公告)号：US11599458B2
公开(公告)日：2023-03-07
申请号：US17551707
申请日：2021-12-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonsik Sohn , Hyunjoong Kim , Woongjae Song , Soowoong Ahn , Seunghyun Cho , Jihyun Choi
IPC: G11C8/00 , G06F12/06 , H01L23/48 , H01L25/065
Abstract: According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.
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公开(公告)号：US11250894B2
公开(公告)日：2022-02-15
申请号：US17145941
申请日：2021-01-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngcheon Kwon , Jemin Ryu , Jaeyoun Youn , Haesuk Lee , Jihyun Choi
Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
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公开(公告)号：US12002543B2
公开(公告)日：2024-06-04
申请号：US18299440
申请日：2023-04-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngcheon Kwon , Jemin Ryu , Jaeyoun Youn , Haesuk Lee , Jihyun Choi
CPC classification number: G11C7/222 , G11C7/1048 , G11C7/1057 , G11C7/1084
Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
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公开(公告)号：US11599301B2
公开(公告)日：2023-03-07
申请号：US17245325
申请日：2021-04-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haesuk Lee , Reum Oh , Youngcheon Kwon , Beomyong Kil , Jemin Ryu , Jihyun Choi
Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.
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公开(公告)号：US11551775B2
公开(公告)日：2023-01-10
申请号：US17313236
申请日：2021-05-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunggi Ahn , Yesin Ryu , Jun Jin Kong , Eunae Lee , Jihyun Choi
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.
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