公开(公告)号：US20200098620A1

公开(公告)日：2020-03-26

申请号：US16411439

申请日：2019-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L21/311

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20240421070A1

公开(公告)日：2024-12-19

申请号：US18409491

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunjung LEE ,  Sanghoon AHN ,  Donggon YOO ,  Jangeun LEE ,  Jeongwon HWANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

公开(公告)号：US20240096796A1

公开(公告)日：2024-03-21

申请号：US18219244

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin KIM ,  Sanghoon AHN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L21/31105

Abstract: An integrated circuit device includes a plurality of wiring structures on a substrate and extending in a first direction parallel to an upper surface of the substrate and each including a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate; an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material; and a capping layer on an upper surface of the wiring layer and including a conductive material; a via layer on the wiring structures, the via layer being electrically connected to one wiring structure; and an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and an upper surface of each insulating pattern.

公开(公告)号：US20190206794A1

公开(公告)日：2019-07-04

申请号：US16296388

申请日：2019-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Sanghoon AHN ,  Nae-In LEE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/306 ,  H01L21/288 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20250126835A1

公开(公告)日：2025-04-17

申请号：US18625457

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin LEE ,  Min Tae RYU ,  Younggeun SONG ,  Sanghoon AHN ,  Min Hee CHO ,  Daewon HA

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

公开(公告)号：US20240087956A1

公开(公告)日：2024-03-14

申请号：US18510732

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20230114920A1

公开(公告)日：2023-04-13

申请号：US18079998

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20230072375A1

公开(公告)日：2023-03-09

申请号：US17984874

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon AHN ,  Woojin LEE ,  Kyuhee HAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

公开(公告)号：US20210166974A1

公开(公告)日：2021-06-03

申请号：US17174409

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Hoon Seok SEO ,  Sanghoon AHN ,  Kyu-Hee HAN

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20210005548A1

公开(公告)日：2021-01-07

申请号：US16742233

申请日：2020-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin LEE ,  Junghoo SHIN ,  Sanghoon AHN ,  Junhyuk LIM ,  Daehan KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.