公开(公告)号：US20160293552A1

公开(公告)日：2016-10-06

申请号：US15048998

申请日：2016-02-19

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Jin YIM ,  Sang-Hoon AHN ,  Thomas OSZINDA ,  Jong-Min BAEK ,  Byung Hee KIM ,  Nae-In LEE ,  Kee-Young JUN

IPC分类号： H01L23/532 ,  H01L23/528

CPC分类号： H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5283 ,  H01L23/53295

摘要： A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

摘要翻译： 半导体器件包括在衬底的第一区域上的绝缘中间层。 绝缘中间层具有凹部，并且包括具有多孔性的低k材料。 在凹部的内表面上形成损伤固化层。 在损伤固化层上形成阻挡图案。 铜结构填充凹部并设置在阻挡图案上。 铜结构包括铜图案和覆盖铜图案表面的铜 - 锰覆盖图案。 可以防止金属在半导体器件的布线结构中的扩散，因此布线结构的电阻可能降低。

公开(公告)号：US20200006269A1

公开(公告)日：2020-01-02

申请号：US16562434

申请日：2019-09-05

申请人： Samsung Electronics Co., Ltd.

发明人： Yi-Koan HONG ,  Kwang-Jin MOON ,  Nae-In LEE ,  Ho-Jin LEE

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

摘要： A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US20130344664A1

公开(公告)日：2013-12-26

申请号：US13973584

申请日：2013-08-22

申请人： Samsung Electronics Co., Ltd.

发明人： Chang-Wook MOON ,  Joong S. JEON ,  Jung-hyun LEE ,  Nae-In LEE ,  Yeon-Sik PARK ,  Hwa-Sung RHEE ,  Ho LEE ,  Se-Young CHO ,  Suk-Pil KIM

IPC分类号： H01L29/66

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  B82Y15/00 ,  H01L21/02365 ,  H01L21/02601 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78684 ,  H01L29/78696 ,  H01L51/426 ,  H01L2221/1094

摘要： A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

摘要翻译： 提供具有至少一个Ge纳米棒的场效应晶体管和制造场效应晶体管的方法。 场效应晶体管可以包括形成在硅衬底上的栅氧化层，至少一个纳米棒嵌入在其两端被暴露的栅极氧化层中，源电极和漏极连接到至少一个Ge纳米棒的相对侧 以及形成在源电极和漏电极之间的栅氧化层上的栅电极。

公开(公告)号：US20180119302A1

公开(公告)日：2018-05-03

申请号：US15797472

申请日：2017-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： Dong-Chan LIM ,  Kwang-Jin MOON ,  Byung-Lyul PARK ,  Nae-In LEE ,  Ho-Jin LEE

IPC分类号： C25D5/00 ,  C25D7/12 ,  C25D17/00 ,  C25D21/12 ,  H01L21/288 ,  H01L21/768

CPC分类号： C25D5/006 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： An electroplating apparatus includes an electroplating bath including an anode installed therein and a plating solution received therein, a substrate holder configured to hold a substrate to be submerged into the plating solution and including a support surrounding the substrate and a cathode on the support to be electrically connected to a periphery of the substrate, a magnetic field generating assembly provided in the support and including at least one electromagnetic coil extending along a circumference of the substrate, and a power supply configured to current to the electromagnetic coil.

公开(公告)号：US20180366671A1

公开(公告)日：2018-12-20

申请号：US15870922

申请日：2018-01-13

申请人： Samsung Electronics Co., Ltd.

发明人： Yi-Koan HONG ,  Kwang-Jin MOON ,  Nae-In LEE ,  Ho-Jin LEE

IPC分类号： H01L51/44 ,  H01L25/065 ,  H01L23/538 ,  H01L23/532 ,  B82Y99/00

CPC分类号： H01L51/444 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/768 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/538 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L51/0048 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/05007 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05693 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/08057 ,  H01L2224/0807 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012

摘要： A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US20170186869A1

公开(公告)日：2017-06-29

申请号：US15406018

申请日：2017-01-13

申请人： Samsung Electronics Co., Ltd.

发明人： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L29/161

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20190206794A1

公开(公告)日：2019-07-04

申请号：US16296388

申请日：2019-03-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Sanghoon AHN ,  Nae-In LEE

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/306 ,  H01L21/288 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC分类号： H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20190189540A1

公开(公告)日：2019-06-20

申请号：US16282682

申请日：2019-02-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jin-Nam Kim ,  Tsukasa MATSUDA ,  Rak-Hwan KIM ,  Byung-Hee KIM ,  Nae-In LEE ,  Jong-Jin LEE

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/522

摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

公开(公告)号：US20180122721A1

公开(公告)日：2018-05-03

申请号：US15661135

申请日：2017-07-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SON-KWAN HWANG ,  Ho-Jin LEE ,  Kwang-Jin MOON ,  Byung-Lyul PARK ,  Jin-Ho AN ,  Nae-In LEE

IPC分类号： H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/485 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311

摘要： A plug structure of a semiconductor chip includes a substrate, an insulating interlayer disposed on the substrate, wherein the insulating interlayer includes a pad structure disposed therein, a via hole penetrating the substrate and the insulating interlayer, wherein the via hole exposes the pad structure, an insulating pattern formed on an interior surface of the via hole, wherein the insulating pattern includes a burying portion, and the burying portion fills a notch disposed in the substrate at the interior surface of the via hole, and a plug formed on the insulating pattern within the via hole, wherein the plug is electrically connected with the pad structure.