X-ray pixels including double photoconductors and X-ray detectors including the X-ray pixels
    1.
    发明授权
    X-ray pixels including double photoconductors and X-ray detectors including the X-ray pixels 有权
    包括双光电导体的X射线像素和包括X射线像素的X射线检测器

    公开(公告)号:US09348037B2

    公开(公告)日:2016-05-24

    申请号:US12923553

    申请日:2010-09-28

    IPC分类号: H01L31/08 G01T1/24

    CPC分类号: G01T1/242 H01L31/085

    摘要: Example embodiments are directed to X-ray detectors including double photoconductors. According to example embodiments, the X-ray detector includes a first photoconductor on which X-rays are incident, and a second photoconductor on which X-rays transmitted through the first photoconductor are incident. The first photoconductor and the second photoconductor include a tandem structure. The first photoconductor is formed of silicon and absorbs X-rays in a low energy band, and the second photoconductor is formed of a material that absorbs X-rays in an energy band higher than the low energy band of the X-rays absorbed by silicon.

    摘要翻译: 示例性实施例涉及包括双光电导体的X射线检测器。 根据示例性实施例,X射线检测器包括在其上入射X射线的第一感光体和通过第一光电导体透射X射线的第二感光体。 第一光电导体和第二光电导体包括串联结构。 第一光电导体由硅形成并在低能带中吸收X射线,第二光电导体由吸收X射线的能量带的材料形成,该能带高于由硅吸收的X射线的低能带 。

    Large-scale X-ray detectors and methods of manufacturing the same
    2.
    发明授权
    Large-scale X-ray detectors and methods of manufacturing the same 有权
    大型X射线探测器及其制造方法

    公开(公告)号:US08847168B2

    公开(公告)日:2014-09-30

    申请号:US12929203

    申请日:2011-01-07

    IPC分类号: G01T1/24 H01L31/08 H01L27/146

    摘要: Large-scale X-ray detectors and methods of manufacturing the same are provided, the large-scale X-ray detectors include a photoconductor layer configured to generate electrical charges according to an incident X-ray using an entire area of the photoconductor layer, a common electrode on an upper surface of the photoconductor layer, a plurality of pixel electrodes, configured to convert the electrical charges into electrical signals, on a lower surface of the photoconductor layer and divided into a plurality of groups, and a plurality of application-specific integrated circuits (ASICs) each corresponding to one of the groups. Each ASIC is configured to process the electrical signals conveyed via the pixel electrodes in the corresponding group. The ASICs process the electrical signals so that seamless image information is collectively generated by the ASICs with respect to the entire area of the photoconductor layer.

    摘要翻译: 提供了大规模X射线检测器及其制造方法,大规模X射线检测器包括:光电导体层,被配置为根据入射的X射线使用光电导体层的整个面积产生电荷; 所述光电导体层的上表面上的公共电极,被配置为将所述电荷转换为电信号的多个像素电极,在所述感光体层的下表面上并分成多个组,以及多个应用特定 集成电路(ASIC),每个对应于该组中的一个。 每个ASIC被配置为处理通过相应组中的像素电极传送的电信号。 ASIC处理电信号,使得ASIC相对于感光体层的整个区域共同地产生无缝图像信息。

    Transistors, methods of manufacturing a transistor, and electronic devices including a transistor
    5.
    发明申请
    Transistors, methods of manufacturing a transistor, and electronic devices including a transistor 有权
    晶体管,制造晶体管的方法以及包括晶体管的电子器件

    公开(公告)号:US20110175080A1

    公开(公告)日:2011-07-21

    申请号:US12805648

    申请日:2010-08-11

    IPC分类号: H01L29/12 H01L29/78 H01L21/16

    摘要: Transistors, methods of manufacturing a transistor, and electronic devices including a transistor are provided, the transistor includes a channel layer, a source and a drain respectively contacting opposing ends of the channel layer, a gate corresponding to the channel layer, a gate insulating layer between the channel layer and the gate, and a first passivation layer and a second passivation layer sequentially disposed on the gate insulating layer. The first passivation layer covers the source, the drain, the gate, the gate insulating layer and the channel layer. The second passivation layer includes fluorine (F).

    摘要翻译: 提供晶体管,制造晶体管的方法和包括晶体管的电子器件,晶体管包括沟道层,分别接触沟道层的相对端的源极和漏极,对应于沟道层的栅极,栅极绝缘层 在沟道层和栅极之间,以及顺序地设置在栅极绝缘层上的第一钝化层和第二钝化层。 第一钝化层覆盖源极,漏极,栅极,栅极绝缘层和沟道层。 第二钝化层包括氟(F)。

    Channel layers and semiconductor devices including the same
    6.
    发明申请
    Channel layers and semiconductor devices including the same 有权
    通道层和包括其的半导体器件

    公开(公告)号:US20100006834A1

    公开(公告)日:2010-01-14

    申请号:US12458491

    申请日:2009-07-14

    IPC分类号: H01L29/26 H01L29/786

    CPC分类号: H01L29/7869 H01L29/78696

    摘要: Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

    摘要翻译: 公开了包括沟道层的通道层和半导体器件。 沟道层可以包括多层结构。 形成沟道层的层可具有不同的载流子迁移率和/或载流子密度。 沟道层可以具有双层结构,其包括可由不同氧化物形成的第一层和第二层。 晶体管的特性可以根据用于形成沟道层的材料和/或其厚度而变化。

    Transistor and method of manufacturing the same
    7.
    发明申请
    Transistor and method of manufacturing the same 有权
    晶体管及其制造方法

    公开(公告)号:US20090224238A1

    公开(公告)日:2009-09-10

    申请号:US12289252

    申请日:2008-10-23

    IPC分类号: H01L29/786 H01L21/336

    CPC分类号: H01L29/7869

    摘要: A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.

    摘要翻译: 根据示例实施例的晶体管可以包括沟道层,分别接触沟道层的端部的源极和漏极,与沟道层分离的栅电极,介于沟道层和栅电极之间的栅极绝缘层和/ 或形成在沟道层和栅极绝缘层之间的插入层。 插入层可以具有与沟道层不同的功函数。

    Stacked memory device and method thereof
    10.
    发明授权
    Stacked memory device and method thereof 有权
    堆叠式存储器件及其方法

    公开(公告)号:US08547719B2

    公开(公告)日:2013-10-01

    申请号:US12588275

    申请日:2009-10-09

    IPC分类号: G11C5/02

    摘要: A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

    摘要翻译: 堆叠存储器件包括多个存储器层,其中多个存储器层中的至少一个堆叠在多个存储器层中的另一个上,并且每个存储器层包括存储器单元阵列,第一有源电路单元配置 将至少一个存储器单元的地址信息分类并处理为垂直地址信息和水平地址信息,以及至少一个第二有源电路单元,配置为基于处理的信号为存储器单元中的至少一个生成存储器选择信号 由第一有源电路单元。