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公开(公告)号：US20090019232A1
公开(公告)日：2009-01-15
申请号：US11776267
申请日：2007-07-11
IPC分类号： G06F12/08
CPC分类号： G06F12/1045 , G06F12/0813 , G06F12/0831
摘要： A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier.
摘要翻译： 处理系统包括多个相干域和多个相干性代理。 每个相关性代理与多个相关域中的至少一个相关联。 在多个相关性代理的选择一致性代理处，使用第一存储器地址来执行一致性消息的地址转换以产生第二存储器地址。 基于地址转换，在选择一致性代理处确定与相关性消息相关联的多个相关性域的选择一致性域。 选择一致性域的一致性消息和一致性域标识符由选择一致性代理提供给一致性互连，用于基于相干域标识符分发给多个相关性代理中的至少一个。
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公开(公告)号：US07941499B2
公开(公告)日：2011-05-10
申请号：US11682867
申请日：2007-03-06
IPC分类号： G06F15/167
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译： 一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。 该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器内消息信息。 系统包括一致性互连和处理器。 处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。 该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息来生成中断。
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公开(公告)号：US20080222389A1
公开(公告)日：2008-09-11
申请号：US11682867
申请日：2007-03-06
IPC分类号： G06F15/76
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译： 一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。 该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器间消息信息。 系统包括一致性互连和处理器。 处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。 该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息生成中断。
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4.发明授权Interrupt controller for accelerated interrupt handling in a data processing system and method thereof 有权用于数据处理系统中加速中断处理的中断控制器及其方法公开(公告)号：US07849247B2
公开(公告)日：2010-12-07
申请号：US12250682
申请日：2008-10-14
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
摘要翻译： 数据处理系统具有中断控制器，其向处理器提供中断请求以及对应的中断标识符和相应的中断向量。 如果处理器接受中断，处理器将通过中断标识符和中断确认返回相同的中断标识符值给中断控制器。 还可以提供中断/未采取的指示符。 用于协调中断控制器和处理器之间的中断处理的通信接口可能是异步的。
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公开(公告)号：US20100095039A1
公开(公告)日：2010-04-15
申请号：US12250682
申请日：2008-10-14
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
摘要翻译： 数据处理系统具有中断控制器，其向处理器提供中断请求以及对应的中断标识符和相应的中断向量。 如果处理器接受中断，处理器将通过中断标识符和中断确认返回相同的中断标识符值给中断控制器。 还可以提供中断/未采取的指示符。 用于协调中断控制器和处理器之间的中断处理的通信接口可能是异步的。
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6.发明授权Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译： 为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。 该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。
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公开(公告)号：US09213665B2
公开(公告)日：2015-12-15
申请号：US12259368
申请日：2008-10-28
CPC分类号： G06F13/4217 , G06F9/3004 , G06F9/30043 , G06F9/3834 , G06F9/3885 , G06F13/16 , G06F2213/0054
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.
摘要翻译： 具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。 诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。 装饰存储通知（DSN）事务包括指令操作的指示，与指令操作相关联的地址和装饰值（即，除了存储或负载之外还执行功能的目标设备的命令）。 系统互连上的事务包括地址阶段和数据阶段，从而提高系统带宽。 在一种形式中，目标设备（例如具有除了存储功能之外的功能的存储器）使用目标设备的存储位置处的信息执行读取 - 修改 - 写入操作。
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8.发明授权Multiple address and arithmetic bit-mode data processing device and methods thereof 有权多地址和算术位模式数据处理装置及其方法公开(公告)号：US07805581B2
公开(公告)日：2010-09-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US20090132796A1
公开(公告)日：2009-05-21
申请号：US11942813
申请日：2007-11-20
IPC分类号： G06F9/318
CPC分类号： G06F9/3009 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.
摘要翻译： 在处理根据轮询循环的指令之前，第一线程进入轮询循环以等待来自第二线程的信号。 当进入轮询循环时，第一线程为预定的存储器地址设置预留。 然后，第一线程执行可以改变第一线程的执行状态的基于预约的指令。 正在执行第一个线程的处理设备的预留电路监视预留。 在保留清除的情况下，例如通过在预定存储器地址处修改数据的第二线程，第一线程被恢复到其先前的执行状态。 通过使用硬件预留机制来监视设定的预约的清除，可以最小化或避免第一线程对存储器地址的重复存储器访问，而在轮询循环中，可以允许其他线程在处理设备处执行减少 来自等待线程的干扰。
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公开(公告)号：US08261047B2
公开(公告)日：2012-09-04
申请号：US12049984
申请日：2008-03-17
IPC分类号： G06F11/36
CPC分类号： G06F9/30076 , G06F9/30189
摘要： A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.
摘要翻译： 处理器实现支持基于其可寻址存储器中的相应地址来选择用于调试指令实例的执行模式可以提供用于以允许指令的某些实例以调试语义来操作的方式来执行调试指令的有吸引力的机制，同时通过 执行它们与无操作（NOP）语义。 在一些实施例中，可操作执行语义的选择可以基于特定调试指令实例驻留在其中的存储器页的属性。 在一些实施例中，地址空间的部分可以被限定（例如，使用存储在边界寄存器中的值和特定调试指令实例的地址与定界部分进行比较以选择适当的执行语义在一些实施例中，可以使用两种类型的评估 在为特定调试指令实例选择适当的执行语义。
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