公开(公告)号：US06493266B1

公开(公告)日：2002-12-10

申请号：US09829193

申请日：2001-04-09

申请人： Santosh K. Yachareni ,  Darlene G. Hamilton ,  Binh Q. Le ,  Kazuhiro Kurihara

发明人： Santosh K. Yachareni ,  Darlene G. Hamilton ,  Binh Q. Le ,  Kazuhiro Kurihara

IPC分类号： G11C1134

CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/3404 ,  G11C16/3436

摘要： A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.

摘要翻译： 公开了用于存储器单元软程序和软程序验证，调整或校正目标最小值与最大值之间的阈值电压的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括将一个参考电压信号施加到过擦除的核心单元，以及将不同的参考电压信号施加到参考单元，比较由每个产生的两个电流，选择性地验证单元的一个或多个位的适当的软编程，确定 双位存储单元被正确软编程。 该方法还可以包括在对该小区的至少一个或多个比特进行选择性软编程之后，选择性地重新验证小区的适当的软编程。

公开(公告)号：US06944057B1

公开(公告)日：2005-09-13

申请号：US10431065

申请日：2003-05-06

申请人： Edward F. Runnion ,  Tien-Chun Yang ,  Binh Quang Le ,  Shigekazu Yamada ,  Darlene G. Hamilton ,  Ming-Huei Shieh ,  Pau-Ling Chen ,  Kazuhiro Kurihara

发明人： Edward F. Runnion ,  Tien-Chun Yang ,  Binh Quang Le ,  Shigekazu Yamada ,  Darlene G. Hamilton ,  Ming-Huei Shieh ,  Pau-Ling Chen ,  Kazuhiro Kurihara

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/10

摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

摘要翻译： 描述了一种用于控制存储器件中的栅极电压的方法。 该方法包括提供适于与存储器件耦合的电路。 该电路用于产生参考电压。 该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。 电压具有对应于存储器件的温度的值。 该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。 参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

公开(公告)号：US08938655B2

公开(公告)日：2015-01-20

申请号：US11961772

申请日：2007-12-20

申请人： Darlene G. Hamilton ,  Mark W. Randolph ,  Don Carlos Darling ,  Ron Kornitz

发明人： Darlene G. Hamilton ,  Mark W. Randolph ,  Don Carlos Darling ,  Ron Kornitz

IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C16/34 ,  G11C16/10

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/3431

摘要： Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.

摘要翻译： 本文公开了通过程序状态改写提供闪速存储器件的扩展数据保存。 作为示例，可以评估存储器单元或存储器单元组以确定单元的程序状态。 如果单元处于编程状态，与自然或非编程状态相反，则可以将充电电平，电压电平和/或类似物重写为与程序状态相关联的默认电平，而不擦除 电池第一。 因此，可以避免用于刷新需要重写和擦除的通常降低存储器单元的存储容量的小区程序状态的常规机制。 结果，存储在闪速存储器中的数据可以以减轻内存完整性损失的方式刷新，相对于可以以相对较高的速率降低存储器完整性的传统机制提供实质的益处。

公开(公告)号：US06967873B2

公开(公告)日：2005-11-22

申请号：US10677790

申请日：2003-10-02

申请人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

发明人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0475 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

公开(公告)号：US06512701B1

公开(公告)日：2003-01-28

申请号：US09886861

申请日：2001-06-21

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Yider Wu

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Yider Wu

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C16/0475 ,  G11C16/0491

摘要： A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.

摘要翻译： 提供了用于验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元的系统和方法。 每个双位具有与第一或正常位相关联的第一或正常位和第二或补充位。 系统和方法包括验证和擦除单元的正常位和互补位。 擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。 该组擦除脉冲由单元或晶体管结中的位的两侧的双侧擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲 。

公开(公告)号：US06331951B1

公开(公告)日：2001-12-18

申请号：US09717550

申请日：2000-11-21

申请人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

发明人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

IPC分类号： G11C1606

CPC分类号： G11C16/344 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3445

摘要： A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.

摘要翻译： 公开了用于验证存储器单元擦除的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括选择性地验证小区的第一比特和小区的第二比特之一的适当擦除，如果小区的第一和第二比特被正确擦除，则确定双比特存储单元被适当地擦除，并且选择性地擦除 如果第一和第二位之一没有被正确擦除，则单元的第一和第二位中的至少一个位。 该方法还可以包括在选择性地擦除第一和第二比特中的至少一个之后，选择性地重新验证第一和第二比特之一的适当擦除。

公开(公告)号：US06307784B1

公开(公告)日：2001-10-23

申请号：US09795856

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Kulachet Tanpairoj ,  Ravi Sunkavalli

发明人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Kulachet Tanpairoj ,  Ravi Sunkavalli

IPC分类号： G11C1600

CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.

摘要翻译： 用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。 该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。 在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。 在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

公开(公告)号：US07626869B2

公开(公告)日：2009-12-01

申请号：US11745327

申请日：2007-05-07

申请人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

发明人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

摘要翻译： 同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。 然而，其他字线不受影响，因为它们在联系人旁边。 因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

公开(公告)号：US07023740B1

公开(公告)日：2006-04-04

申请号：US10755979

申请日：2004-01-12

申请人： Nga-Ching Wong ,  Darlene G. Hamilton

发明人： Nga-Ching Wong ,  Darlene G. Hamilton

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.

摘要翻译： 用于编程非易失性存储器的衬底偏置的方法和系统。 在包括用于非易失性存储单元的沟道区的阱下的深阱结构中施加偏置电压。 在编程期间，施加到深阱的负偏压有利地在通道区域内产生电子的不均匀分布，在通道区域的表面具有大量电子。 向控制栅极和漏极施加额外的偏置电压可能导致电子从沟道区迁移到非易失性存储单元的存储层。 有利地，由于在通道区域的表面处的电子供应增加，非易失性电池的编程比常规技术更快。

公开(公告)号：US06788583B2

公开(公告)日：2004-09-07

申请号：US10307749

申请日：2002-12-02

申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

IPC分类号： G11C1606

CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。