公开(公告)号：US07281073B2

公开(公告)日：2007-10-09

申请号：US10727147

申请日：2003-12-03

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: G06F13/24

CPC classification number: G06F13/26

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract translation: 辅助中断控制电路用于包括用于产生中断请求的至少一个外围设备的计算机系统，用于存储中断请求的中断挂起寄存器，用于处理中断的微处理器以及与微处理器相关联的中断控制电路。 辅助控制电路可以包括耦合到优先中断寄存器的辅助寄存器，用于存储中断请求的副本。 它可以进一步包括耦合到辅助寄存器和微处理器的编码器，用于产生标识对应于要处理的最高优先级中断请求的辅助寄存器中存储的有效位的位串，并用于向微处理器提供位串。

公开(公告)号：US06735514B2

公开(公告)日：2004-05-11

申请号：US09977563

申请日：2001-10-15

Applicant: Alessandro Pepi ,  Saverio Pezzini ,  Paolo Marceca ,  Alberto Ferrari

Inventor： Alessandro Pepi ,  Saverio Pezzini ,  Paolo Marceca ,  Alberto Ferrari

IPC: G06F1900

CPC classification number: G11C7/1045 ,  F02D41/2422 ,  F02D41/2435 ,  F02D41/266 ,  G11C16/102

Abstract: A control device for a vehicle engine includes a memory unit for storing engine configuration parameters, a processing unit for sending control signals to the engine in accordance with the configuration parameters, and an input/output unit connectible to an external computer to modify the configuration parameters. The control device includes a first portion and a second portion of the memory unit, with each portion being alternately used in an active state for storing a current version of the configuration parameters or in an inactive state for the writing of a new version of the configuration parameters. The processing unit accesses the portion which is in the active state for reading, and the input/output unit accesses the portion which is in the inactive state for writing. An interconnection unit selectively switches one of the portions to the active state and the other of the portions to the inactive state.

Abstract translation: 一种用于车辆发动机的控制装置，包括用于存储发动机配置参数的存储单元，用于根据配置参数向发动机发送控制信号的处理单元，以及可连接到外部计算机的输入/输出单元，以修改配置参数 。 控制装置包括存储器单元的第一部分和第二部分，其中每个部分交替地用于活动状态，用于存储当前版本的配置参数，或处于非活动状态，用于写入新版本的配置 参数。 处理单元访问处于用于读取的活动状态的部分，并且输入/输出单元访问处于非活动状态的部分进行写入。 互连单元选择性地将部分中的一个切换到活动状态，将另一部分切换到非活动状态。

公开(公告)号：US07120718B2

公开(公告)日：2006-10-10

申请号：US10717177

申请日：2003-11-19

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.

Abstract translation: 一种用于产生微处理器系统的中断命令的方法包括将中断存储在等待中断寄存器中，以及将与所存储的中断相关联的优先级值存储在耦合到等待中断寄存器的多个优先级寄存器中。 耦合到多个优先级寄存器的多个计数器被加载存储的优先级值。 加载的优先级值以预定间隔递增，并且被比较以识别具有最高优先级的中断。 该方法还包括基于具有最高优先级的中断识别要执行的相应中断服务程序。

公开(公告)号：US07203781B2

公开(公告)日：2007-04-10

申请号：US10744700

申请日：2003-12-23

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.

Abstract translation: 微处理器系统包括高速主总线，耦合到高速主总线的多个主设备以及耦合到高速主总线的多个外设。 外设包括至少一个内存。 仲裁器电路耦合到高速主总线，用于管理任何一个主设备对高速主总线的访问请求。 微处理器系统还包括辅助总线以及耦合在高速主总线和辅助总线之间的桥接器电路。 桥接口电路包括直接存储器存取控制器，使得在连接到辅助总线的外围设备和其中一个外围设备之间的每个数据传输程序期间减少到高速主总线的单次传送阶段接合。

公开(公告)号：US07069352B2

公开(公告)日：2006-06-27

申请号：US10634150

申请日：2003-08-04

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: A serial interface for communicating with peripherals may include a circuit for generating pointers to addresses in sections of a memory, and a circuit for serially transferring data from or to at least one peripheral connected to the interface that is coupled to the memory based upon requisite configuration commands. The interface may further include a control register coupled to the memory and to the serial transfer circuit for controlling data to be transmitted or received. The interface does not require that an external controller provide configuration commands each time data is transmitted or received because the memory sections for storing data may be divided in distinct memory spaces. That is, each memory space may store data for a respective peripheral connected to the interface. Moreover, another memory section may be used to store all of the configuration commands of the interface required for communicating with the peripherals.

Abstract translation: 用于与外围设备进行通信的串行接口可以包括用于在存储器的部分中产生指向地址的指针的电路，以及用于根据必要配置，连接到连接到接口的至少一个外围设备的串行数据传输数据的电路 命令。 接口还可以包括耦合到存储器和串行传输电路的控制寄存器，用于控制要发送或接收的数据。 该接口不要求外部控制器在每次发送或接收数据时都提供配置命令，因为用于存储数据的存储器部分可以分成不同的存储空间。 也就是说，每个存储器空间可以存储连接到接口的相应外设的数据。 此外，可以使用另一个存储器部分来存储与外围设备进行通信所需的接口的所有配置命令。

公开(公告)号：US5579196A

公开(公告)日：1996-11-26

申请号：US267145

申请日：1994-06-27

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: G06F12/16 ,  G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  H02H3/18

CPC classification number: G11C5/147

Abstract: A protection circuit (1) comprising a first and second supply line at a first and second supply voltage respectively; a reference voltage source; a comparator connected to the first supply line and the source; and a switch controlled by the comparator via a control terminal and located between the second supply line and the output of the circuit. To reduce static consumption of the comparator under normal operating conditions, the circuit comprises enabling control elements connected to the two supply lines and to the comparator for disabling the comparator and turning on the switch when the two supply voltages differ by a value below a predetermined threshold, but are greater than a reference value.

Abstract translation: 一种保护电路（1），分别包括第一和第二电源电压的第一和第二电源线; 参考电压源; 比较器，连接到第一电源线和源; 以及由比较器经由控制端控制并位于第二电源线和电路的输出之间的开关。 为了在正常工作条件下降低比较器的静电消耗，该电路包括使两个电源电压连接的控制元件与比较器相连使得禁止比较器和导通开关，当两个电源电压相差低于一个预定阈值 ，但大于参考值。

公开(公告)号：US20060190765A1

公开(公告)日：2006-08-24

申请号：US11344538

申请日：2006-01-30

Applicant: Nicolas Grossier ,  Chilakala Kumar ,  Saverio Pezzini

Inventor： Nicolas Grossier ,  Chilakala Kumar ,  Saverio Pezzini

IPC: G06F11/00

CPC classification number: G06F8/66 ,  G06F9/328

Abstract: A system for correcting errors in read-only memory devices by means of memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in the memory. The system includes a processing core, such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses being patched. The processing core is configured for providing different patch-data for correcting errors depending on whether it is performing a code access or a data access to an address being patched.

Abstract translation: 一种用于通过存储器补丁校正只读存储器件中的错误的系统，其中补丁数据被用作代替存储在存储器中给定位置的错误数据的读取数据。 该系统包括诸如ARM处理器的处理核心，其适于执行操作码访问以及对正在被修补的存储器地址的数据访问。 处理核心被配置用于根据其是执行代码访问还是对要修补的地址的数据访问来提供用于校正错误的不同补丁数据。

公开(公告)号：US06873272B2

公开(公告)日：2005-03-29

申请号：US10713541

申请日：2003-11-14

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1076 ,  H03M1/12

Abstract: An integrated circuit includes an input pad for receiving an externally generated analog signal, and a pre-sampling circuit for pre-sampling at least one internally generated analog reference signal. An analog-to-digital converter is connected to the input pad for providing a numerical value of the externally generated analog signal, and is connected to the pre-sampling circuit for providing a numerical value of the internally generated analog reference signal. A fault signaling circuit is connected to the pre-sampling circuit and to the analog-to-digital converter for generating a fault signal when the numerical value of the externally generated analog signal is equal to the numerical value of the internally generated analog reference signal. The fault signal indicates that an electrical connection providing the externally generated analog signal to the input pad is faulty.

Abstract translation: 集成电路包括用于接收外部产生的模拟信号的输入焊盘和用于对至少一个内部产生的模拟参考信号进行预采样的预采样电路。 模拟 - 数字转换器连接到输入焊盘，用于提供外部产生的模拟信号的数值，并连接到预采样电路，以提供内部产生的模拟参考信号的数值。 当外部产生的模拟信号的数值等于内部产生的模拟参考信号的数值时，故障信号电路连接到预采样电路和模拟 - 数字转换器，用于产生故障信号。 故障信号表示向输入焊盘提供外部产生的模拟信号的电气连接有故障。

公开(公告)号：US6124821A

公开(公告)日：2000-09-26

申请号：US119901

申请日：1998-07-21

Applicant: Saverio Pezzini ,  Paolo Brasca

Inventor： Saverio Pezzini ,  Paolo Brasca

IPC: H03M1/06 ,  H03M1/80 ,  H03M1/38

CPC classification number: H03M1/0648 ,  H03M1/806

Abstract: A capacitive array particularly for converters, comprising a plurality of unitary capacitors, the number of the unitary capacitors being equal to 2.sup.n, where n is the number of bits of the binary code required in output, the unitary capacitors being mutually connectable so as to obtain capacitors in which the capacitance ratio between one capacitor and the adjacent parallel-connected capacitor is equal to a factor of two. The invention is that the factor-of-two capacitance ratio of adjacent capacitors is achieved by mutually diagonally connecting in parallel the unitary-capacitance capacitors of the capacitive array in a preset number according to the capacitance value to be obtained.

Abstract translation: 特别是用于转换器的电容阵列，包括多个单体电容器，单体电容器的数量等于2n，其中n是输出中所需的二进制码的位数，单位电容器是可互相连接的，从而获得 其中一个电容器和相邻的并联电容器之间的电容比等于二的电容器。 本发明是相邻的电容器的二次电容比通过根据要获得的电容值以预先设定的数值并联并联电容阵列的单电容电容器来实现的。

公开(公告)号：US5774646A

公开(公告)日：1998-06-30

申请号：US280761

申请日：1994-07-26

Applicant: Saverio Pezzini ,  Roberto Ganzelmi ,  Maurizio Peri

Inventor： Saverio Pezzini ,  Roberto Ganzelmi ,  Maurizio Peri

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  H01L21/82 ,  G06F11/20

CPC classification number: G11C29/70 ,  G11C29/24 ,  G11C29/44

Abstract: A method whereby the N elements of a memory are read sequentially, and the data items contained therein are compared with reference data items. Simultaneously with the reading of each element of the memory, its address is written in a number of redundancy check registers, each connected to a respective redundancy element. In the event the element of the memory differs from the reference data item, the first of the redundancy check registers is blocked to prevent it from being overwritten and the address of a faulty element of the memory is permanently stored. Upon the entire memory being read, the addresses of any faulty elements in the memory are thus already stored in the redundancy check registers.

Abstract translation: 将存储器的N个元素顺序读取并将其中包含的数据项与参考数据项进行比较的方法。 与存储器的每个元件的读取同时，其地址被写入多个冗余校验寄存器中，每个冗余校验寄存器连接到相应的冗余元件。 在存储器的元素与参考数据项不同的情况下，第一冗余校验寄存器被阻塞以防止其被覆盖，并且存储器的故障元素的地址被永久存储。 在读取整个存储器时，存储器中任何故障元件的地址因此已经存储在冗余校验寄存器中。