公开(公告)号：US06304107B1

公开(公告)日：2001-10-16

申请号：US09513018

申请日：2000-02-25

申请人： Scott C. Savage ,  Rick F. Bitting

发明人： Scott C. Savage ,  Rick F. Bitting

IPC分类号： H03K524

CPC分类号： H03K5/249

摘要： A detection circuit for receiving a pair of unstable input signals along a pair of input leads and providing a stable output signal along an output lead, preferably to downstream circuitry. The detection circuit includes a plurality of transistors including a first transistor and a second transistor, wherein at least one of the first and second transistors is configured to turn on upon the detection circuit receiving input signals along the pair of input leads. At least one of the first and second transistors is configured to provide a signal along a lead to circuitry which is configured to condition the output signal and turn on a third transistor. The third transistor is connected to the first and said second transistors such that when the third transistor turns on, the third transistor prevents the first and second transistors from turning on until a new clock signal is received by the detection circuit. Thus, the third transistor generally prevents any new input signals received along the input leads from propagating substantially through the detection circuit. Large differential hysteresis prevents small signals from propagating. The third transistor effectively limits the time period for decision making.

摘要翻译： 一种检测电路，用于沿着一对输入引线接收一对不稳定的输入信号，并且沿输出引线优选地向下游电路提供稳定的输出信号。 检测电路包括包括第一晶体管和第二晶体管的多个晶体管，其中第一和第二晶体管中的至少一个被配置为在检测电路沿着该对输入引线接收输入信号时导通。 第一晶体管和第二晶体管中的至少一个被配置为沿着引线向电路提供信号，该电路被配置为调节输出信号并接通第三晶体管。 第三晶体管连接到第一和第二晶体管，使得当第三晶体管导通时，第三晶体管防止第一和第二晶体管导通，直到检测电路接收到新的时钟信号。 因此，第三晶体管通常防止沿着输入引线接收的任何新的输入信号基本上传播通过检测电路。 大的差分滞后可防止小信号传播。 第三个晶体管有效地限制了决策的时间。

公开(公告)号：US07272802B2

公开(公告)日：2007-09-18

申请号：US11126880

申请日：2005-05-11

申请人： Donald T. McGrath ,  Scott C. Savage

发明人： Donald T. McGrath ,  Scott C. Savage

IPC分类号： G06F17/50

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H03K19/173 ,  H01L2924/00

摘要： A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step of the method may be to design a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form an electrostatic discharge clamp at a power domain crossing. A third step may include second fabricating the chip to add the upper metal layers.

摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括首先制造仅包括第一金属层并且包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 该方法的第二步可以是响应于在第一制造开始之后产生的定制设计，在第一金属层上方设计多个上金属层，上金属层将多个单元互连以形成静电放电 夹在电源交叉口。 第三步骤可以包括第二制造芯片以添加上金属层。

公开(公告)号：US06242897B1

公开(公告)日：2001-06-05

申请号：US09497652

申请日：2000-02-03

申请人： Scott C. Savage ,  Ricky F. Bitting

发明人： Scott C. Savage ,  Ricky F. Bitting

IPC分类号： G05F316

CPC分类号： G05F3/30

摘要： An on-chip voltage reference supply operates in the current domain rather than the voltage domain, implemented with a single diode drop to reduce power supply headroom requirements. A plurality of current generators generate currents representing a first design voltage. A gain circuit responds to the currents to supply a gain voltage representing the sum of the first design voltages. A summing circuit sums the gain voltage and a second design voltage to derive the predetermined reference voltage.

摘要翻译： 片上电压参考电源在电流域中运行，而不是电压域，采用单个二极管降压实现，以减少电源余量要求。 多个电流发生器产生表示第一设计电压的电流。 增益电路响应电流以提供表示第一设计电压之和的增益电压。 求和电路将增益电压和第二设计电压相加以导出预定的参考电压。

公开(公告)号：US07478354B2

公开(公告)日：2009-01-13

申请号：US11133815

申请日：2005-05-20

申请人： Donald T. McGrath ,  Scott C. Savage ,  Robert D. Waldron ,  Kenneth G. Richardson

发明人： Donald T. McGrath ,  Scott C. Savage ,  Robert D. Waldron ,  Kenneth G. Richardson

IPC分类号： G06F17/50

CPC分类号： H01L27/118 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.

摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括在第一制造阶段期间仅制造直到并包括第一金属层的芯片，使得芯片的输入/输出（I / O）区域具有多个槽，其中， 槽具有多个第一晶体管。 该方法的第二步可以包括响应于在第一制造开始之后创建的定制设计来设计在第一金属层上方的多个上金属层，上金属层将多个第一晶体管互连以形成多个 混合信号构建块功能。 该方法的第三步可以涉及制造芯片以在第二制造阶段添加上金属层。

公开(公告)号：US07360178B2

公开(公告)日：2008-04-15

申请号：US11136180

申请日：2005-05-24

申请人： Scott C. Savage ,  Donald T. McGrath ,  Robert D. Waldron ,  Kenneth G. Richardson

发明人： Scott C. Savage ,  Donald T. McGrath ,  Robert D. Waldron ,  Kenneth G. Richardson

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.

摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括仅制造直到并包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 第二步通常包括响应于在第一制造开始之后产生的定制设计而在第一金属层之上设计多个上金属层，上金属层互连多个单元以形成（i）混合信号 模块和（ii）数字模块，所述混合信号模块产生至少一个模拟信号和至少一个数字信号。 在第三步骤中，该方法可以包括制造芯片以添加上部金属层。

公开(公告)号：US06313668B1

公开(公告)日：2001-11-06

申请号：US09536527

申请日：2000-03-28

申请人： Scott C. Savage

发明人： Scott C. Savage

IPC分类号： G11C2702

CPC分类号： G11C27/026 ,  H03H19/004

摘要： A sample and hold in a switched capacitor circuit with frequency shaping. The sample and hold does not require a pair of large area, power-consuming operational amplifiers and, as such, consumes less power and less area. Preferably, the sample and hold is operable in four different states wherein a different set of switches are closed in each of the four states. The switches are controlled by two clock signals and a plurality of signals derived from the two clock signals, such as four signals derived from the two clock signals. Desirably, the sample and hold with frequency shaping is configured to sample a voltage across a first capacitor while a second capacitor is disconnected from said first capacitor, and is configured to thereafter connect the second capacitor to the first capacitor and possibly discharge at least a portion of a charge held in the first capacitor into the second capacitor.

摘要翻译： 采样并保持在具有频率整形的开关电容电路中。 采样和保持不需要一对大面积的耗电运算放大器，因此消耗更少的功率和更少的面积。 优选地，采样和保持可操作在四种不同状态，其中在四种状态的每一种状态下闭合不同的开关组。 开关由两个时钟信号和从两个时钟信号导出的多个信号（例如从两个时钟信号导出的四个信号）控制。 期望地，具有频率整形的采样和保持被配置为在第二电容器与所述第一电容器断开的同时对第一电容器的电压进行采样，并且被配置为此后将第二电容器连接到第一电容器并且可能将至少一部分 保持在第一电容器中的电荷进入第二电容器。

公开(公告)号：US07566923B2

公开(公告)日：2009-07-28

申请号：US11318332

申请日：2005-12-23

申请人： Donald T. McGrath ,  Gregory Winn ,  Scott C. Savage

发明人： Donald T. McGrath ,  Gregory Winn ,  Scott C. Savage

IPC分类号： H01L27/118

CPC分类号： H03K19/1736 ,  H01L27/0207 ,  H01L27/11807

摘要： A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

摘要翻译： 一种包括基础层的平台专用集成电路（ASIC）。 基本层通常包括预定义的输入/输出（I / O）区域和预定义的核心区域。 预定义的输入/输出（I / O）区域可以包括布置在平台ASIC中的多个预扩散区域。 预定义的芯区域可以包括一个或多个限定根据在制造基层之后创建的定制设计形成的多个功率区域的金属层。 可以通过沉积一个或多个金属层来定制基层。

公开(公告)号：US07259586B2

公开(公告)日：2007-08-21

申请号：US11115561

申请日：2005-04-27

申请人： Scott A. Peterson ,  Donald T. McGrath ,  Scott C. Savage ,  Kenneth G. Richardson

发明人： Scott A. Peterson ,  Donald T. McGrath ,  Scott C. Savage ,  Kenneth G. Richardson

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/1735 ,  H03K19/17732 ,  H03K19/17788 ,  H03K19/17796

摘要： An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.

摘要翻译： 一种包括集成电路和逻辑部分的装置。 集成电路可以具有多个区域，每个区域（i）预扩散并被配置为金属编程，并且（ii）被配置为将集成电路连接到插座。 逻辑部分可以在集成电路上实现。 多个金属可编程区域各自（i）可独立编程，并且（ii）位于所述预扩散区域之一中。 每个金属可编程区域包括：（a）调节器部分，被配置为从公共电源电压产生工作电压，（b）逻辑部分，被配置为实现集成电路功能并在工作电压下工作，以及（c） 移位器被配置为将工作电压转换到外部电压电平。

公开(公告)号：US07081841B1

公开(公告)日：2006-07-25

申请号：US11117682

申请日：2005-04-28

申请人： Douglas J. Feist ,  Scott C. Savage ,  Kevin J. Gearhardt

发明人： Douglas J. Feist ,  Scott C. Savage ,  Kevin J. Gearhardt

IPC分类号： H03M1/20

CPC分类号： H03M1/108 ,  H03M1/12

摘要： A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.

摘要翻译： 内置自检电路，用于测试模数转换器。 上计数器接收测试输入和第一个时钟信号，并提供和上限。 下降计数器接收测试输入和第一个时钟信号，并提供下限。 数模转换器接收测试输入和第二时钟信号，并提供模拟输出。 电路将模拟输出和第三时钟信号提供给模数转换器，因此模数转换器产生数字信号。 上限比较器接收上限和数字信号，并提供指示数字信号是否违反上限的上限状态信号。 下限比较器接收下限和数字信号，并提供指示数字信号是否违反下限的下限状态信号。

公开(公告)号：US06768339B2

公开(公告)日：2004-07-27

申请号：US10194650

申请日：2002-07-12

申请人： Matthew S. Von Thun ,  Scott C. Savage

发明人： Matthew S. Von Thun ,  Scott C. Savage

IPC分类号： H03K190175

CPC分类号： H03K19/00315 ,  H03K17/162 ,  H03K17/6872 ,  H03K2217/0018 ,  H03K2217/0054

摘要： An apparatus comprising (i) an input circuit configured to provide a predetermined voltage tolerance in response to a plurality of control signals and (ii) a control circuit configured to generate the plurality of control signals in response to one or more input signals.